Article

LiPaR: A light-weight parallel router for FPGA-based networks-on-chip

Authors:

Balasubramanian Sethuraman,

Prasun Bhattacharya,

Ranga VemuriAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 452 - 457

https://doi.org/10.1145/1057661.1057769

Published: 17 April 2005 Publication History

Abstract

Present day technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. The latest FPGAs can support only about 10 million gates to accomodate all logic and the associated routing. In order to implement a competitive NoC architecture in FP-GAs, the area occupied by the network should be kept to a minimum. This ensures that the maximum area can be utilized by the logic while maintaining the performance of the router network. Reducing area also reduces the power consumption. In this paper, we implement a parallel router which can support five simultaneous routing requests at the same time with an area overhead of only 352 Xilinx Virtex-II Pro FPGA slices (2. 57% of XC2VP30). We introduce optimizations in XY routing and decoding logic thereby gaining in area and performance. The header overhead is 8 bits per packet and the packet size can vary between 16 and 128 bits. We also implement a 3 x 3 mesh network with a total area overhead of 28% leaving 72% of the area available for the logic in a Virtex-II Pro XC2VP30 device. We characterize the router and several mesh networks for power and performance parameters.

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Cited By

Nikolić SNikolić S(2025)Time-Domain-Multiplexed InterconnectModern Programmable Interconnect Design10.1007/978-3-031-80629-2_9(285-311)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_9
Swarbrick IGaitonde DAhmad SGaide BArbel YBazargan KNeuendorffer S(2019)Network-on-Chip Programmable Platform in VersalTM ACAP ArchitectureProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293908(212-221)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293908
Chen YGurumani SLiang YLi GGuo DRupnow KChen D(2016)FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA FlowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.249725924:6(2220-2233)Online publication date: Jun-2016
https://doi.org/10.1109/TVLSI.2015.2497259
Show More Cited By

Index Terms

LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
1. Hardware
  1. Integrated circuits
    1. Interconnect

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Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 April 2005

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April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Nikolić SNikolić S(2025)Time-Domain-Multiplexed InterconnectModern Programmable Interconnect Design10.1007/978-3-031-80629-2_9(285-311)Online publication date: 7-Mar-2025
https://doi.org/10.1007/978-3-031-80629-2_9
Swarbrick IGaitonde DAhmad SGaide BArbel YBazargan KNeuendorffer S(2019)Network-on-Chip Programmable Platform in VersalTM ACAP ArchitectureProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293908(212-221)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293908
Chen YGurumani SLiang YLi GGuo DRupnow KChen D(2016)FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA FlowIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.249725924:6(2220-2233)Online publication date: Jun-2016
https://doi.org/10.1109/TVLSI.2015.2497259
Abdelfattah MBetz V(2016)Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom BusesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239700524:1(165-177)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2397005
Maidee PKaviani A(2015)Improving FPGA NoC performance using virtual cut-through switching technique2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393323(1-6)Online publication date: Dec-2015
https://doi.org/10.1109/ReConFig.2015.7393323
Brugge MKhalid M(2014)A Parameterizable NoC Router for FPGAsJournal of Computers10.4304/jcp.9.3.519-5289:3Online publication date: 1-Mar-2014
https://doi.org/10.4304/jcp.9.3.519-528
Abdelfattah MBetz V(2014)Networks-on-Chip for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26294427:3(1-22)Online publication date: 3-Sep-2014
https://dl.acm.org/doi/10.1145/2629442
Schleuniger PKarlsson S(2014)A Synthesizable Multicore Platform for Microwave ImagingReconfigurable Computing: Architectures, Tools, and Applications10.1007/978-3-319-05960-0_18(197-204)Online publication date: 2014
https://doi.org/10.1007/978-3-319-05960-0_18
Mandal AKhatri SMahapatra RMacii E(2013)Exploring topologies for source-synchronous ring-based network-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485535(1026-1031)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485535
Pham-Quoc CHeisswolf JWerner SAl-Ars ZBecker JBertels KMacii E(2013)Hybrid interconnect design for heterogeneous hardware acceleratorsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485491(843-846)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485491
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