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Efficient partitioning of fragment shaders for multiple-output hardware

Published: 29 August 2004 Publication History

Abstract

Partitioning fragment shaders into multiple rendering passes is an effective technique for virtualizing shading resource limits in graphics hardware. The Recursive Dominator Split (RDS) algorithm is a polynomial-time algorithm for partitioning fragment shaders for real-time rendering that has been shown to generate efficient partitions. RDS does not, however, work for shaders with multiple outputs, and does not optimize for hardware with support for multiple render targets.We present Merging Recursive Dominator Split (MRDS), an extension of the RDS algorithm to shaders with arbitrary numbers of outputs which can efficiently utilize hardware support for multiple render targets, as well as a new cost metric for evaluating the quality of multipass partitions on modern consumer graphics hardware. We demonstrate that partitions generated by our algorithm execute more efficiently than those generated by RDS alone, and that our cost model is effective in predicting the relative performance of multipass partitions.

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  • (2019)Specialization Opportunities in Graphical WorkloadsProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00029(271-282)Online publication date: 23-Sep-2019
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      cover image ACM Conferences
      HWWS '04: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
      August 2004
      142 pages
      ISBN:3905673150
      DOI:10.1145/1058129
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 29 August 2004

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      GH04: Graphics Hardware 2004
      August 29 - 30, 2004
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      View all
      • (2024)GPU Coroutines for Flexible Splitting and Scheduling of Rendering TasksACM Transactions on Graphics10.1145/368776643:6(1-24)Online publication date: 19-Nov-2024
      • (2019)Specialization Opportunities in Graphical WorkloadsProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00029(271-282)Online publication date: 23-Sep-2019
      • (2008)Control flow emulation on tiled SIMD architecturesProceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction10.5555/1788374.1788384(100-115)Online publication date: 29-Mar-2008
      • (2008)Control Flow Emulation on Tiled SIMD ArchitecturesCompiler Construction10.1007/978-3-540-78791-4_7(100-115)Online publication date: 2008
      • (2006)The CGiS compiler—a tool demonstrationProceedings of the 15th international conference on Compiler Construction10.1007/11688839_10(105-108)Online publication date: 30-Mar-2006
      • (2005)Optimal automatic multi-pass shader partitioning by dynamic programmingProceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware10.1145/1071866.1071881(91-98)Online publication date: 30-Jul-2005
      • (2004)MioProceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware10.1145/1058129.1058135(35-44)Online publication date: 29-Aug-2004

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