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Proceedings of the 2nd conference on Computing frontiers table of contents
Ischia, Italy
SESSION: Part 3: adiabatic and energy-recovery circuits table of contents
Pages: 407 - 413  
Year of Publication: 2005
ISBN:1-59593-019-1
Authors
Visvesh Sathe  University of Michigan, Ann Arbor, MI
Juang-Ying Chueh  University of Michigan, Ann Arbor, MI
Joohee Kim  University of Michigan, Ann Arbor, MI
Conrad H. Ziesler  MultiGig, Inc., Scotts Valley, CA
Suhwan Kim  Seoul National University, Seoul, Korea
Marios C. Papaefthymiou  University of Michigan, Ann Arbor, MI
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at sub-stantially lower power dissipation levels than their conventional counterparts. In this paper, we present two such chips that were designed in our research group and highlight some of the promising charge-recovery techniques in practice. Although their origins can be traced back to the early adiabatic circuits, these techniques approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in excess of 1GHz with relatively low overheads


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Amer, M. Bolotski, P. Alvelda, and T. Knight. A 160x120 pixel liquid-crystal-on-silicon microdisplay with an adiabatic dac. In IEEE International Solid-State Circuits Conference, November 1999.
 
2
W. Athas, N. Tzartzanis, W. Mao, L. Peterson, R. Lal, K. Chong, J.-S. Moon, L. Svensson, and M. Bolotski. The design and implmementation of a low-power clock-powered microprocessor. IEEE Journal of Solid-State Circuits, SC-35(11):1561--1570, November 2000.
 
3
W. C. Athas, N. Tzartzanis, L. J. Svensson, and L. Peterson. A low-power microprocessor based on resonant energy. IEEE Journal of Solid-State Circuits, SC-32(11):1693--1701, November 1997.
 
4
C. H. Bennett and R. Landauer. The fundamental physical limits of computation. Scientific American, 253(1):38--46, July 1985.
 
5
J. Chueh, C. Ziesler, and M. Papaefthymiou. Two-phase resonant clock distribution. In Unpublished Manuscript, 2005.
 
6
7
8
9
 
10
 
11
A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson, and T. R. Wik. Adiabatic computing with the 2N-2N2D logic family. In Digest of Technical Papers of IEEE Symposium on VLSI Circuits, pages 25--26, April 1994.
12
 
13
J. Lim, D. Kim, and S. Chae. A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. IEEE Journal of Solid-State Circuits, SC-34(6):898--903, June 1999.
 
14
 
15
Y. Moon and D. Jeong. An efficient charge recovery logic circuit. IEEE Journal of Solid-State Circuits, SC-31(4):514--522, April 1996.
 
16
Y. Moon and D. K. Jeong. A 32x32-b adiabatic register file with supply clock generator. IEEE Journal of Solid-State Circuits, SC-33(5):696--701, May 1998.
 
17
V. G. Oklobdzija and D. Maksimovic. Pass-transistor adiabatic logic using single power-clock supply. IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 44(10):842--846, October 1997.
 
18
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2):305--327, February 2003.
 
19
V. Sathe, C. Ziesler, and M. Papaefthymiou. Boost logic: A high speed energy recovery circuit family. In Unpublished Manuscript, 2005.
 
20
D. Somasekhar, Y. Ye, and K. Roy. An energy recovering static RAM memory core. In Proceedings of International Symposium on Low Power Design, April 1995.
 
21
N. Tzartzanis, W.C. Athas, and L. Svensson. A low-power SRAM with resonantly powered data, address, word, and bit lines. In European Solid-State Circuits Conference, 2000.
 
22
 
23
J. Wood, T. Edwards, and S. Lipa. Rotary travelling-wave oscillator arrays: a new clock technology. IEEE Journal of Solid-State Circuits, SC-36(11):1654--1665, November 2001.
 
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Collaborative Colleagues:
Visvesh Sathe: colleagues
Juang-Ying Chueh: colleagues
Joohee Kim: colleagues
Conrad H. Ziesler: colleagues
Suhwan Kim: colleagues
Marios C. Papaefthymiou: colleagues