skip to main content
article

Demystifying on-the-fly spill code

Published: 12 June 2005 Publication History

Abstract

Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that register requirements increase significantly because values across different loop iterations can be live concurrently. One possible solution to reduce register pressure is to insert spill code to release registers. Spill code stores values to memory between the producer and consumer instructions.Spilling heuristics can be divided into two classes: 1) a posteriori approaches (spill code is inserted after scheduling the loop) or 2) on-the-fly approaches (spill code is inserted during loop scheduling). Recent studies have reported obtaining better results for spilling on-the-fly. In this work, we study both approaches and propose two new techniques, one for each approach. Our new algorithms try to address the drawbacks observed in previous proposals. We show that the new algorithms outperform previous techniques and, at the same time, reduce compilation time. We also show that, much to our surprise, a posteriori spilling can be in fact slitghtly more effective than on-the-fly spilling.

References

[1]
V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger. Clock rate versus ipc: the end of the road for conventional microarchitectures. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 248--259, June 2000.
[2]
A. Aletà, J. M. Codina, J. Sánchez, and A. Gonález. Graph partitioning based instruction scheduling for clustered processors. In Proceedings of the 34th International Symposium on Microarchitecture, pages 150--159, December 2001.
[3]
A. Aletà, J. M. Codina, J. Sánchez, A. Gonález, and D. Kaeli. Exploiting pseudo-schedules to guide data dependence graph partitioning. In Proceedings of the International Conference on Parallel Architectures and Compiler Techniques, pages 281--290, September 2002.
[4]
G. Chaitin. Register allocation and spilling via graph coloring. ACM SIGPLAN Notices, 39(4):66--74, April 2004.
[5]
J. M. Codina, J. Sánchez, and A. González. A unified modulo scheduling and register allocation technique for clustered processors. In Proceedings of the International Conference on Parallel Architectures and Compiler Techniques, pages 175--184, September 2001.
[6]
J. Dehnert, P. Hsu, and J. Bratt. Overlapped loop support in the cydra 5. In Proceedings of the 3rd International conference on architectural support for programming languages and operating systems, pages 26--38, April 1989.
[7]
P. Faraboschi, G. Brown, J. Fisher, G. Desoli, and F. Homewood. Lx: a technology platform for customizable vliw embedded processubg. In Proceedings of the 27th international symposium on computer architecutre, June 2000.
[8]
J. Fridman and Z. Greenfield. The tigersharc dsp architecture. IEEE Micro, pages 66--76, January-february 2000.
[9]
P. Glaskowsky. Map1000 unfolds at equator. Microprocessor report, 12(16), December 1998.
[10]
R. Ju, S. Chan, T.-F. Ngai, C. Wu, Y. Lu, and J. Zhang. Open research compiler (orc) 2.0 and tuning performance on itanium. Presented at the 35th International Symposium on Microarchitecture, December 2002.
[11]
J. Llosa, E. Ayguadé, A. González, and M. Valero. Swing modulo scheduling. In Proceedings of the International Conference on Parallel Architectures and Compiler Techniques, September 1996.
[12]
J. Llosa, M. Valero, and E. Ayguadé. Heuristics for register-constrained software pipelining. In Proceedings of the 29th International Symposium on Microarchitecture, pages 250--261, December 1996.
[13]
G. G. Pechanek and S. Vassiliadis. The manarray embedded processor architecture. In Proceedings of the 26th Euromicro Conference: Informatics: inventing the future, September 2000.
[14]
B. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register allocation for software pipelined loops. In Proceedings of the conference on Programming language design and implementation, pages 283--299, June 1992.
[15]
B. R. Rau. Iterative modulo scheduling: an algorithm for software pipelining loops. In Prceedings of the 27th annual international symposium on Microarchitecture, pages 63 -- 74, November 1994.
[16]
J. Ruttenberg, G. R. Gao, A. Stoutchinin, and W. Lichtenstein. Software pipelining showdown: optimal vs. heuristic methods in a production compiler. In Proceedings of the conference on programming language design and implementation, pages 1--11, May 1996.
[17]
TexasInstrumentsInc. TMS320C62x/67x CPU and instruction set reference guide, 1998.
[18]
J. Wand, A. Krall, M. A. Ertl, and C. Eisenbeis. Software pipelining with register allocation and spilling. In Proceedings of the 27th International Symposium on Microarchitecture, pages 95--99, November 1994.
[19]
J. Zalamea, J. Llosa, E. Ayguadé, and M. Valero. Improved spill code generation for software pipelined loops. In Proceedings of the conference on programming language design and implementation, pages 134--144, June 2000.
[20]
J. Zalamea, J. Llosa, E. Ayguadé, and M. Valero. Mirs: Modulo scheduling with integrated register spilling. In Proceedings of the 14th workshop on languages and compilers for parallel computing, august 2001.

Cited By

View all
  • (2007)Register allocation and optimal spill code scheduling in software pipelined loops using 0-1 integer linear programming formulationProceedings of the 16th international conference on Compiler construction10.5555/1759937.1759949(126-140)Online publication date: 26-Mar-2007
  • (2007)Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming FormulationCompiler Construction10.1007/978-3-540-71229-9_9(126-140)Online publication date: 2007
  • (2009)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420043839.ch19(19-1-19-57)Online publication date: 7-Dec-2009

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 40, Issue 6
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
June 2005
325 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1064978
Issue’s Table of Contents
  • cover image ACM Conferences
    PLDI '05: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
    June 2005
    338 pages
    ISBN:1595930566
    DOI:10.1145/1065010
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 June 2005
Published in SIGPLAN Volume 40, Issue 6

Check for updates

Author Tags

  1. modulo scheduling
  2. register allocation
  3. spill code

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)2
  • Downloads (Last 6 weeks)0
Reflects downloads up to 02 Mar 2025

Other Metrics

Citations

Cited By

View all
  • (2007)Register allocation and optimal spill code scheduling in software pipelined loops using 0-1 integer linear programming formulationProceedings of the 16th international conference on Compiler construction10.5555/1759937.1759949(126-140)Online publication date: 26-Mar-2007
  • (2007)Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming FormulationCompiler Construction10.1007/978-3-540-71229-9_9(126-140)Online publication date: 2007
  • (2009)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420043839.ch19(19-1-19-57)Online publication date: 7-Dec-2009

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media