Article

Variability and energy awareness: a microarchitecture-level perspective

Authors:

Diana Marculescu,

Emil TalpesAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 11 - 16

https://doi.org/10.1145/1065579.1065588

Published: 13 June 2005 Publication History

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Abstract

This paper proposes microarchitecture-level models for Within Die (WID) process and system parameter variability that can be included in the design of high-performance processors. Since decisions taken at microarchitecture level have the largest impact on both performance and power, on one hand, and global variability effect, on the other hand, models and associated metrics are needed for their joint characterization and analysis. To assess how these variations affect or are affected by microarchitecture decisions, we propose a joint performance, power and variability metric that is able to distinguish among various design choices. As a design-driver for the modeling methodology, we consider a clustered high-performance processor implementation, along with its Globally Asynchronous, Locally Synchronous (GALS) counterpart. Results show that, when comparing the baseline, synchronous and its GALS counterpart, microarchitecture-driven impact of process variability translates into 2-10% faster local clocks for the GALS case, while when taking into account the effect of on-chip temperature variability, local clocks can be 8-18% faster. If, in addition, voltage scaling (DVS) is employed, the GALS architecture with DVS is 26% better in terms of the joint quality metric employing energy, performance, and variability.

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Cited By

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Reif SHerzog BHügel FHönig TSchröder-Preikschat WKim TLee P(2020)Nearly symmetric multi-core processorsProceedings of the 11th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3409963.3410486(42-49)Online publication date: 24-Aug-2020
https://dl.acm.org/doi/10.1145/3409963.3410486
Nittala RAcquaviva AMacii E(2017)A Software Toolchain for Variability Awareness on Heterogenous Multicore PlatformsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25625985:1(95-107)Online publication date: 1-Jan-2017
https://doi.org/10.1109/TETC.2016.2562598
Cai EMarculescu D(2017)Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266672136:11(1897-1910)Online publication date: Nov-2017
https://doi.org/10.1109/TCAD.2017.2666721
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Index Terms

Variability and energy awareness: a microarchitecture-level perspective
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Hardware validation

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Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 2005

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June 13 - 17, 2005

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Reif SHerzog BHügel FHönig TSchröder-Preikschat WKim TLee P(2020)Nearly symmetric multi-core processorsProceedings of the 11th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3409963.3410486(42-49)Online publication date: 24-Aug-2020
https://dl.acm.org/doi/10.1145/3409963.3410486
Nittala RAcquaviva AMacii E(2017)A Software Toolchain for Variability Awareness on Heterogenous Multicore PlatformsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25625985:1(95-107)Online publication date: 1-Jan-2017
https://doi.org/10.1109/TETC.2016.2562598
Cai EMarculescu D(2017)Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.266672136:11(1897-1910)Online publication date: Nov-2017
https://doi.org/10.1109/TCAD.2017.2666721
Stamoulis DMarculescu D(2016)Can We Guarantee Performance Requirements under Workload and Process Variations?Proceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934641(308-313)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934641
Kozhikkottu VVenkatesan RRaghunathan ADey S(2016)Emulation-Based Analysis of System-on-Chip Performance Under VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.255124324:12(3401-3414)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1109/TVLSI.2016.2551243
Darwish MCalayir VPileggi LWeldon J(2016)Ultracompact Graphene Multigate Variable Resistor for Neuromorphic ComputingIEEE Transactions on Nanotechnology10.1109/TNANO.2016.252503915:2(318-327)Online publication date: Mar-2016
https://doi.org/10.1109/TNANO.2016.2525039
Rahimi ABenini LGupta R(2016)Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to SoftwareProceedings of the IEEE10.1109/JPROC.2016.2518864104:7(1410-1448)Online publication date: Jul-2016
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Cai EMarculescu DMarculescu DLiu F(2015)TEI-TurboProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840889(500-507)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840889
Ayad GNittala RLemaire R(2015)Automatic Runtime Customization for Variability Awareness on Multicore PlatformsProceedings of the 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip10.1109/MCSoC.2015.19(143-150)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1109/MCSoC.2015.19
Kozhikkottu VVenkataramani SDey SRaghunathan AXie YKarnik TKhellah MMehra R(2014)Variation tolerant design of a vector processor for recognition, mining and synthesisProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627636(239-244)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2627636
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Abstract

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Exploiting selective instruction reuse and value prediction in a superscalar architecture

Bypass aware instruction scheduling for register file power reduction

Reducing instruction bit-width for low-power VLIW architectures

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