Enhanced leakage reduction Technique by gate replacement

ABSTRACT

Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additional logic gates can be inserted as control points to make it more effective. In this paper, we propose a gate replacement technique that further enhances the leakage reduction. The basic idea is to replace a gate that is in its worst leakage state by another library gate while keeping the circuit's correct functionality at the active mode. We also develop a divide-and-conquer approach that integrates a fast gate replacement heuristic, an optimal MLV search strategy for tree circuit, and a genetic algorithm to connect the tree circuits. We conduct experiments on the MCNC91 benchmark circuits. The results reveal that our technique can reduce additional 10% to 24% leakage over the best known IVC methods and the optimal MLV with no delay penalty and little area increase.

REFERENCES

• 1: Afshin Abdollahi , Farzan Fallah , Massoud Pedram, Leakage current reduction in CMOS VLSI circuits by input vector control, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.140-154, February 2004 [doi>10.1109/TVLSI.2003.821546]
• 2: Fadi A. Aloul , Soha Hassoun , Karem A. Sakallah , David Blaauw, Robust SAT-Based Search Algorithm for Leakage Power Reduction, Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, p.167-177, September 11-13, 2002
• 3: Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871535]
• 4: David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin, Evaluating Run-Time Techniques for Leakage Power Reduction, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.31, January 07-11, 2002
• 5: Feng Gao , J. P. Hayes, Exact and heuristic approaches to input vector control for leakage power reduction, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.527-532, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382634]
• 6: J. Halter, and F. Najm, "A Gate-Level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits", CICC, pp 475--478, 1997.
• 7: M.C. Johnson, D. Somasekhar, and K. Roy, "Models and Algorithms for Bounds on Leakage in CMOS Circuits", IEEE Trans. on CAD, Vol. 18, pp. 714--725, 1999.
• 8: James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774593]
• 9: Rahul M. Rao , Frank Liu , Jeffrey L. Burns , Richard B. Brown, A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.689, November 09-13, 2003 [doi>10.1109/ICCAD.2003.9]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
MLV, gate replacement, leakage reduction