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Navigating registers in placement for clock network minimization

Published: 13 June 2005 Publication History

Abstract

The progress of VLSI technology is facing two limiting factors: power and variation. Minimizing clock network size can lead to reduced power consumption, less power supply noise, less number of clock buffers and therefore less vulnerability to variations. Previous works on clock network minimization are mostly focused on clock routing and the improvements are often limited by the input register placement. In this work, we propose to navigate registers in cell placement for further clock network size reduction. To solve the conflict between clock network minimization and traditional placement goals, we suggest the following techniques in a quadratic placement framework: (1) Manhattan ring based register guidance; (2) center of gravity constraints for registers; (3) pseudo pin and net; (4) register cluster contraction. These techniques work for both zero skew and prescribed skew designs in both wirelength driven and timing driven placement. Experimental results show that our method can reduce clock net wirelength by 16%~33% with no more than 0.5% increase on signal net wirelength compared with conventional approaches.

References

[1]
D. E. Duate, N. Vijaykrishnan and M. J. Irwin, "A clock power model to evaluate impact of architectural and technology optimization," in IEEE TVLSI, 10(6): 844--855, Dec. 2002.
[2]
S. Zhao, K. Roy and C.-K. Koh, "Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits," in Proc. IEEE ICCD, pp. 65--72, 2000.
[3]
S. Zanella, A. Nardi, A. Neviani, M. Quarantelli, S. Saxena and C. Guardiani, "Analysis of the impact of process variations on clock skew," in IEEE Transactions on Semiconductor Manufacturing, 13(4): 401--407, Nov. 2000.
[4]
T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese and A. B. Kahng, "Zero skew clock routing with minimum wirelength," in IEEE Transactions on Circuits & Systems II: Analog &Digital Signal Processing, 39 (11): 799--814, Nov. 1992.
[5]
J. Cong, A. B. Kahng, C.-K. Koh and C.-W. A. Tsao, "Bounded-skew clock and Steiner routing," in ACM TODAES, 3(3): 341--388, Jul. 1998.
[6]
R. Chaturvedi and J. Hu, "A simple yet effective merging scheme for prescribed-skew clock routing," in Proc. IEEE ICCD, pp. 282--287, 2003.
[7]
C.-W. A. Tsao and C.-K. Koh, "UST/DME: a clock tree router for general skew constraints," in Proc. IEEE/ACM ICCAD, pp. 400--405, 2000.
[8]
R. B. Deokar and S. S. Sapatnekar, "A graph-theoretic approach to clock skew optimization", in Proc. IEEE ISCAS, pp.1.407--1.410, 1994.
[9]
J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," in IEEE TCAD, 10(3): 356--365, Mar. 1991.
[10]
M. Wang and M. Sarrafzadeh, "Congestion minimization during placement," in Proc. ACM ISPD, pp. 145--150, 1999.
[11]
W. Hou, X. Hong, W. Wu and Y. Cai, "A path-based timingdriven quadratic placement algorithm," in Proc. IEEE/ACM ASP-DAC, pp.745--748, 2003.
[12]
Y. Liu, X. Hong, Y. Cai, W. Wu, "CEP: A clock-driven ECO placement algorithm for standard-cell layout," in Proc. International Conference on ASIC, pp. 118--121, 2001.
[13]
N. Venkateswaran and D. Bhatia, "Clock-skew constrained placement for row based designs," in Proc. IEEE ICCD, pp. 219--220, 1998.
[14]
B. Kernighan and S. Lin. "An Efficient Heuristic Procedure for Partitioning of Electrical Circuits". Bell System Technical Journal, pp. 291--307, 1970.
[15]
A. E. Dunlop and B. W. Kernighan, "A procedure for placement of standard-cell VLSI circuits," IEEE TCAD, vol. CAD-4, pp. 92--98, Jan. 1985.
[16]
N. Viswanathan and C.-N Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," in Proc. ACM ISPD, pp. 26--33, 2004.

Cited By

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  • (2023)Power Consumption in CMOS CircuitsElectromagnetic Field in Advancing Science and Technology10.5772/intechopen.105717Online publication date: 29-Mar-2023
  • (2023)Clock Aware Low Power Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323626(01-08)Online publication date: 28-Oct-2023
  • (2021)Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel ProtectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302493840:6(1077-1089)Online publication date: Jun-2021
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    cover image ACM Conferences
    DAC '05: Proceedings of the 42nd annual Design Automation Conference
    June 2005
    984 pages
    ISBN:1595930582
    DOI:10.1145/1065579
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 13 June 2005

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    Author Tags

    1. clock network
    2. low power
    3. placement
    4. variation tolerance

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    June 13 - 17, 2005
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    Cited By

    View all
    • (2023)Power Consumption in CMOS CircuitsElectromagnetic Field in Advancing Science and Technology10.5772/intechopen.105717Online publication date: 29-Mar-2023
    • (2023)Clock Aware Low Power Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323626(01-08)Online publication date: 28-Oct-2023
    • (2021)Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel ProtectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302493840:6(1077-1089)Online publication date: Jun-2021
    • (2019)CAD4EM-P: Security-Driven Placement Tools for Electromagnetic Side Channel Protection2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST47458.2019.9006705(1-6)Online publication date: Dec-2019
    • (2016)Flip-flop clustering by weighted K-means algorithmProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898025(1-6)Online publication date: 5-Jun-2016
    • (2016)Clock-Tree-Aware Incremental Timing-Driven PlacementACM Transactions on Design Automation of Electronic Systems10.1145/285879321:3(1-27)Online publication date: 19-Apr-2016
    • (2016)A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architectureInternational Journal of Circuit Theory and Applications10.1002/cta.227745:4(550-570)Online publication date: 24-Oct-2016
    • (2015)Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237698834:2(280-292)Online publication date: Feb-2015
    • (2015)Progress and Challenges in VLSI Placement ResearchProceedings of the IEEE10.1109/JPROC.2015.2478963103:11(1985-2003)Online publication date: Nov-2015
    • (2015)Crosstalk-aware multi-bit flip-flop generation for power optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2014.08.00248:C(146-157)Online publication date: 1-Jan-2015
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