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Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits

Published: 13 June 2005 Publication History

Abstract

Reliability of nanometer circuits is becoming a major concern in today's VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft errors. Traditional noise analysis/avoidance and manufacturing testing are no longer sufficient to handle the dynamic interactions between various noise sources and unpredictable operational variations. Therefore, "robustness insertion" has been adopted as the supplementary approach to ensure high circuit reliability through on-line protections. However, the related design overhead is not always acceptable, especially for cost/timing-sensitive designs. In this paper, we present a novel "constraint-aware robustness insertion" methodology protect the sequential elements in digital circuits against various noise effects. Based on a configurable hardening sequential cell design and an efficient sequential cell robustness estimation technique, an optimization algorithm is developed to search for the optimal protection scheme under given timing and area constraints. Experiment results demonstrate that the proposed methodology is able to achieve a high degree of noise-tolerance while keeping the protection cost within limit.

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      cover image ACM Conferences
      DAC '05: Proceedings of the 42nd annual Design Automation Conference
      June 2005
      984 pages
      ISBN:1595930582
      DOI:10.1145/1065579
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 13 June 2005

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      Author Tags

      1. circuit hardening
      2. nanometer circuits
      3. robustness calibration
      4. robustness insertion

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