ABSTRACT
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower non-optimal supply voltage which can underestimate the energy/ operation by 8.2X. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures.
- J. Schutz and C. Webb. A scalable X86 CPU design for 90nm process. ISSCC, 2004.Google Scholar
- A. P. Chandrakasan and R. W. Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995. Google ScholarDigital Library
- D. Liu and C. Svensson. Trading speed for low power by choice of supply and threshold voltages. IEEE Journal of Solid-State Circuits, 28(1):10--17, January 1993.Google ScholarCross Ref
- C. Kim, H. Soeleman, and K. Roy. Ultra-low-power DLMS adaptive filter for hearing aid applications. IEEE Transactions on VLSI, 11(6):1058--1067, December 2003. Google ScholarDigital Library
- M. Eisele,, et al. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Transactions on VLSI, 5(4):360--368, December 1997. Google ScholarDigital Library
- D. Boning and S. Nassif. Models of process variations in device and interconnect. In A. Chandrakasan, W. J. Bowhill, and F. Fox, editors, Design of High-Performance Microprocessor Circuits. IEEE Press, New York, NY, 2001.Google Scholar
- http://www-device.eecs.berkeley.edu/~ptm/.Google Scholar
- D. Lee, W. Kwong, D. Blaauw, and D. Sylvester. Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design. ISQED, pages 287--292, 2003. Google ScholarDigital Library
- W.K. Henson et al. Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime. IEEE Transactions on Electron Devices, 47(2):440--447, February 2000.Google Scholar
- Y.L. Tong. The Multivariate Normal Distribution. Springer-Verlang, 1990.Google ScholarCross Ref
- B.H. Calhoun, A. Wang, and A. Chandrakasan. Device sizing for minimum energy operation in subthreshold circuits. Custom Integrated Circuits Conference, 2003.Google Scholar
Index Terms
- Variations-aware low-power design with voltage scaling
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