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A code compression advisory tool for embedded processors

Published: 13 March 2005 Publication History

Abstract

We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-time random decompression. Given the machine instruction set architecture, the encoding of instructions, and a set of object programs to be compressed, the tool analyzes the code, gathers statistics about static instruction frequencies and other relevant information, and performs a relative evaluation of a suite of compression strategies. The tool produces as output, the sizes of the compressed code, the Line Address Table (if one is required), and the dictionary (if there is only one) or the sizes of all dictionaries if there are several, for various choices of parameters input by the user. The final result helps one to decide a code compression strategy for the input processor. We have used the tool to evaluate alternate schemes for a suite of benchmarks for the TI TMS320C62x instruction set architecture and the Intel StrongARM processor and report results.

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Vinodh Cuppu and Bruce L. Jacob. Simulator for Texas Instruments TMS320C62x. http://www.glue.umd.edu/ ramvinod/c6xsim-1.1.tar.gz.
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Cited By

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  • (2014)Studying the code compression design space - A synthesis approachJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.11.00160:2(179-193)Online publication date: 1-Feb-2014
  • (2012)An Efficient Tool-Chain for Analyzing Tradeoffs of Code Compression Schemes in Embedded ProcessorsProceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2012.35(192-201)Online publication date: 19-Aug-2012

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cover image ACM Conferences
SAC '05: Proceedings of the 2005 ACM symposium on Applied computing
March 2005
1814 pages
ISBN:1581139640
DOI:10.1145/1066677
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 March 2005

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Author Tags

  1. code compression
  2. embedded system tool
  3. run time decompression

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SAC05
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SAC05: The 2005 ACM Symposium on Applied Computing
March 13 - 17, 2005
New Mexico, Santa Fe

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Cited By

View all
  • (2014)Studying the code compression design space - A synthesis approachJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.11.00160:2(179-193)Online publication date: 1-Feb-2014
  • (2012)An Efficient Tool-Chain for Analyzing Tradeoffs of Code Compression Schemes in Embedded ProcessorsProceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2012.35(192-201)Online publication date: 19-Aug-2012

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