David W. Wall
- 1.Tilak Agarwala and John Cocke. High performance reduced instruction set processors. IBM Thomas J. Watson Research Center Technical Report #55845, March 31, 1987.Google Scholar
- 2.David R. Chase, Mark Wegman, and F. Kenneth Zadeck. Analysis of pointers and structures. Proceedings of the SIGPLAN '90 Conference on Programming Language Design and Implementation, pp. 296-310. Published as SIGPLAN Notices 25 (6), June 1990. Google ScholarDigital Library
- 3.Jack J. Dongarra. Performance of various computers using standard linear equations software in a Fortran environment. Computer Architecture News 11 (5), pp. 22-27, December 1983. Google ScholarDigital Library
- 4.Joseph A. Fisher, John R. Ellis, John C. Ruttenberg, and Alexandru Nicolau. Parallel processing: A smart compiler and a dumb machine. Proceedings of the SIG- PLAN '84 Symposium on Compiler Construction, pp. 37-47. Published as SIGPLAN Notices 19 (6), June 1984. Google ScholarDigital Library
- 5.John Hennessy. Stanford benchmark suite. Personal communication.Google Scholar
- 6.eil D. Jones and Steven S. Muchnick. A flexible approach to interprocedural data flow analysis and programs with recursive data structures. Ninth Annual ACM Symposium on Principles of Programming Languages, pp. 66-74, Jan. 1982. Google ScholarDigital Library
- 7.Norman P. Jouppi and David W. Wall. Available instruction-level parallelism for superscalar and superpipelined machines. Third International Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 272-282, April 1989. Published as Computer Architecture News 17 (2), Operating Systems Review 23 (special issue), SIGPLAN Notices 24 (special issue). Also available as WRL Research Report 89/7. Google ScholarDigital Library
- 8.Monica Lain. Software pipelining: An effective scheduling technique for VLIW machines. Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation, pp. 318-328. Published as SIGPLAN Notices 23 (7), July 1988. Google ScholarDigital Library
- 9.Johnny K. F. Lee and Alan J. Smith. Branch prediction strategies and branch target buffer design. Computer 17 (1), pp. 6-22, January 1984.Google ScholarDigital Library
- 10.Scott McFarling and John Hennessy. Reducing the cost of branches. Thirteenth Annual Symposium on Computer Architecture, pp. 396-403. Published as Computer Architecture News 14 (2), June 1986. Google ScholarDigital Library
- 11.Alexandru Nicolau and Joseph A. Fisher. Measuring the parallelism available for very long instruction word architectures. IEEE Transactions on Computers C-33 (11), pp. 968-976, November 1984.Google ScholarDigital Library
- 12.J.E. Smith. A study of branch prediction strategies. Eighth Annual Symposium on Computer Architecture, pp. 135-148. Published as Computer Architecture News 9 (3), 1986. Google ScholarDigital Library
- 13.Michael D. Smith, Mike Johnson, and Mark A. Horowitz. Limits on multiple instruction issue. Third International Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 290-302, April 1989. Published as Computer Architecture News 17 (2), Operating Systems Review 23 (special issue), SIGPLAN Notices 24 (special issue). Google ScholarDigital Library
- 14.G.S. Tjaden and M. J. Flynn. Detection and parallel execution of parallel instructions. IEEE Transactions on Computers C-19 (10), pp. 889-895, October 1970.Google ScholarDigital Library
Index Terms
- Limits of instruction-level parallelism
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Instruction-level parallelism
Encyclopedia of Computer ScienceInstruction-level parallelism (ILP) is a set of processor and compiler design techniques that speed up program execution via the parallel execution of individual RISC-style operations, such as memory loads and stores, integer additions, and floating-...
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP) and thread-level parallelism (TLP). Wide-issue super-scalar processors exploit ILP by executing multiple instructions from a ...
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