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A fast, energy-efficient z-comparator

Published: 30 July 2005 Publication History

Abstract

We present a fast and energy-efficient z-comparator that takes advantage of the fact that the result of most depth comparisons can be determined by examining just a few bits. This feature is made possible by the use of asynchronous logic, which enables the comparator to rapidly compare bits until the result is clear and then stop. Using depth data from well-known computer games, SPICE simulations indicate that our comparator consumes only 25% of the energy and operates 1.67 times faster, on average, compared to an equivalent synchronous design. The comparator design is used to illustrate a more general design principle, "compute on demand," which can potentially enable graphics hardware to be faster and more energy-efficient.

References

[1]
{BJN99} Berkel C. H. K. V., Josephs M. B., Nowick S. M.: Scanning the technology: Applications of asynchronous circuits. Proc. of the IEEE 87, 2 (Feb. 1999), 223--233.
[2]
{ECKM05} Ekanayake V. N., Clinton Kelly I., Manohar R.: Bitsnap: Dynamic significance compression for a low-energy sensor network asynchronous processor. In ASYNC(2005) (2005), IEEE Computer Society, pp. 144--154.
[3]
{KS95} Knittel G., Schilling A.: Eliminating the z-buffer bottleneck. In EDTC '95: Proceedings of the 1995 European conference on Design and Test (Washington, DC, USA, 1995), IEEE Computer Society, p. 12.
[4]
{Mes} Mesa3d graphics library. http:/mesa3d.org.
[5]
{NYB97} Nowick S. M., Yun K. Y., Beerel P. A.: Speculative completion for the design of high-performance asynchronous dynamic adders. In ASYNC (Apr. 1997), pp. 210--223.
[6]
{PKEG04} Ponomarev D., Kucuk G., Ergin O., Ghose K.: Energy efficient comparators for superscalar datapaths. IEEE Transactions on Computers 53, 7 (July 2004), 892--904.
[7]
{RSG*99} Rotem S., Stevens K., Ginosar R., Beerel P., Myers C., Yun K., Kol R., Dike C., Roncken M., Agapiev B.: RAPPID: An asynchronous instruction length decoder. In ASYNC (Apr. 1999), pp. 60--70.
[8]
{STR*02} Singh M., Tierno J. A., Rylyakov A., Rylov S., Nowick S. M.: An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz. In ASYNC (Manchester, UK, Apr. 2002).
[9]
{WE93} Weste N., Eshraghian K.: Priniciples of CMOS VLSI Design, a Systems Perspective, second ed. Addison-Wesley Publishing Co., 1993.
[10]
{WLWW03} Wang C.-C., Lee P.-M., Wu C.-F., Wu H.-L.: High fan-in dynamic cmos comparators with low transistor count. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (2003).
[11]
{YBV*97} Yun K. Y., Beerel P. A., Vakilotojar V., Dooply A. E., Arceo J.: The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. In ASYNC (Apr. 1997), pp. 140--153.

Cited By

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  • (2021)VLSI Implementation of a High Speed and Area efficient N-bit Digital CMOS Comparator2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE)10.1109/ICSTCEE54422.2021.9708574(1-4)Online publication date: 16-Dec-2021
  • (2020)A Modified Inter-Stage Binary Comparator Based on Parallel Prefix for Low Power and High-Density Applications2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON50219.2020.9376557(1-6)Online publication date: 27-Nov-2020
  • (2020) High‐speed and area‐efficient scalable N ‐bit digital comparator IET Circuits, Devices & Systems10.1049/iet-cds.2018.556214:4(450-458)Online publication date: 10-Mar-2020
  • Show More Cited By

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    cover image ACM Conferences
    HWWS '05: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
    July 2005
    121 pages
    ISBN:1595930868
    DOI:10.1145/1071866
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 30 July 2005

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    GH05: Graphics Hardware 2005
    July 30 - 31, 2005
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    HWWS '05 Paper Acceptance Rate 13 of 32 submissions, 41%;
    Overall Acceptance Rate 50 of 126 submissions, 40%

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    View all
    • (2021)VLSI Implementation of a High Speed and Area efficient N-bit Digital CMOS Comparator2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE)10.1109/ICSTCEE54422.2021.9708574(1-4)Online publication date: 16-Dec-2021
    • (2020)A Modified Inter-Stage Binary Comparator Based on Parallel Prefix for Low Power and High-Density Applications2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON50219.2020.9376557(1-6)Online publication date: 27-Nov-2020
    • (2020) High‐speed and area‐efficient scalable N ‐bit digital comparator IET Circuits, Devices & Systems10.1049/iet-cds.2018.556214:4(450-458)Online publication date: 10-Mar-2020
    • (2015)A novel floating point comparator using parallel tree structure2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]10.1109/ICCPCT.2015.7159395(1-6)Online publication date: Mar-2015
    • (2013)Scalable Digital CMOS Comparator Using a Parallel Prefix TreeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.222245321:11(1989-1998)Online publication date: 1-Nov-2013

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