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A segmented parallel-prefix VLSI circuit with small delays for small segments
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Source ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures table of contents
Las Vegas, Nevada, USA
SESSION: Brief announcements table of contents
Pages: 213 - 213  
Year of Publication: 2005
ISBN:1-58113-986-1
Author
Bradley C. Kuszmaul  MIT CSAIL, Cambridge, Massachusetts
Sponsors
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 4,   Citation Count: 0
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ABSTRACT

I present a VLSI circuit for segmented parallel prefix with gate delay O(log S) and wire delay.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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B. C. Kuszmaul. A segmented parallel-prefix vlsi circuit with small delays for small segments (full version). http://kuszmaul.net/p/Kuszmaul05b, MAY 2005.
 
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B. C. Kuszmaul, D. S. Henry, and G. H. Loh. A comparison of asymptotically scalable superscalar processors. Theory of Comput. Syst., 35:129--150, 2002.
 
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Collaborative Colleagues:
Bradley C. Kuszmaul: colleagues