| Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2005 international symposium on Low power electronics and design
table of contents
San Diego, CA, USA
SESSION: Technologies and devices for low power
table of contents
Pages: 26 - 29
Year of Publication: 2005
ISBN:1-59593-137-6
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Authors
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Ali Keshavarzi
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Circuit Research Lab, Intel Corporation, Hillsboro, OR
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Gerhard Schrom
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Circuit Research Lab, Intel Corporation, Hillsboro, OR
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Stephen Tang
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Circuit Research Lab, Intel Corporation, Hillsboro, OR
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Sean Ma
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University of Arizona, Tucson, AZ
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Keith Bowman
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TCAD, Intel Corporation, Hillsboro, OR
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Sunit Tyagi
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Portland Technology Development, Intel Corporation, Hillsboro, OR
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Kevin Zhang
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Portland Technology Development, Intel Corporation, Hillsboro, OR
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Tom Linton
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TCAD, Intel Corporation, Hillsboro, OR
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Nagib Hakim
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TCAD, Intel Corporation, Hillsboro, OR
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Steven Duvall
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TCAD, Intel Corporation, Hillsboro, OR
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John Brews
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University of Arizona, Tucson, AZ
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Vivek De
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Circuit Research Lab, Intel Corporation, Hillsboro, OR
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Downloads (6 Weeks): 2, Downloads (12 Months): 57, Citation Count: 1
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 ABSTRACT
Fluctuations in intrinsic linear Vt, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic σVT, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. Meindl, et. al., 1997 ISSCC, pp. 232--233.
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P. Stolk, et. al., IEEE TED, 45 (9), 1998. pp. 1960--1970.
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T. Mizuno, et. al., IEEE TED, 41 (11), 1994, pp. 2216--2221.
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D. Burnett, et. al., 1994 VLSI Technology Symposium, pp.15--16.
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INDEX TERMS
Primary Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.0
General
Additional Classification:
B.
Hardware
B.8
Performance and Reliability
B.8.0
General
General Terms:
Design,
Measurement,
Performance,
Theory
Keywords:
CMOS,
Vt,
Vt mismatch,
Vt variation,
body bias,
integrated circuits,
mismatch,
process variation,
random dopant variation,
threshold voltage,
threshold voltage variation,
transistor mismatch,
transistor threshold voltage mismatch,
transistors,
variation
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