Low-power fanout optimization using multiple threshold voltage inverters

ABSTRACT

This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, power, and input capacitance, the fanout tree is converted to a set of inverter chains and for each chain the optimal sizes and threshold voltages are determined. Experimental results show that using this technique, the power dissipation of fanout tree is reduced by an average of 33% for a state-of-the-art CMOS technology.

REFERENCES

• 1: C. Leonard Berman , J. Lawrence Carter , Ken F. Day, The fanout problem: from theory to practice, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.69-99, June 1989, Cambridge, Massachusetts, United States
• 2: K. Kodandapani , J. Grodstein , A. Domic , H. Touati, A simple algorithm for fanout optimization using high-performance buffer libraries, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.466-471, November 07-11, 1993, Santa Clara, California, United States
• 3: David S. Kung, A fast fanout optimization algorithm for near-continuous buffer libraries, Proceedings of the 35th annual conference on Design automation, p.352-355, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277143]
• 4: Rezvani, P. and Pedram, M. A fanout optimization algorithm based on the effort delay model. IEEE Trans. on Computer-Aided Design, 22, (Dec. 2003), 1671--1678.
• 5: Sakurai, T. and Newton, A.R. A simple MOSFET model for circuit analysis. IEEE Trans. Electron Device, 38, (Apr. 1991), 887--894.
• 6: De, V., et al. Techniques for leakage power reduction in Chandrakasan, A., et al., Design of High-Performance Microprocessor Circuits. IEEE press, NJ, 2001, 46--62.
• 7: Vaidya, P. M. A new algorithm for minimizing convex functions over convex sets. In Proc. IEEE Foundations Comput. Sci., 1989, 332--337.
• 8: Vijay Sundararajan , Keshab K. Parhi, Low power synthesis of dual threshold voltage CMOS VLSI circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.139-144, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313900]
• 9: Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2003 edition, http://public.itrs.net/.
• 10: Ankur Srivastava, Simultaneous Vt selection and assignment for leakage optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871543]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Performance

Keywords:
buffer chain, fanout optimization, fanout tree, low-power design