| Defocus-aware leakage estimation and control |
| Full text |
Pdf
(190 KB)
|
| Source
|
International Symposium on Low Power Electronics and Design
archive
Proceedings of the 2005 international symposium on Low power electronics and design
table of contents
San Diego, CA, USA
SESSION: Power grid, thermal, and leakage issues
table of contents
Pages: 263 - 268
Year of Publication: 2005
ISBN:1-59593-137-6
|
|
Authors
|
|
Andrew B. Kahng
|
University of California at San Diego, San Diego, CA
|
|
Swamy Muddu
|
University of California at San Diego, San Diego, CA
|
|
Puneet Sharma
|
University of California at San Diego, San Diego, CA
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 39, Citation Count: 1
|
|
|
ABSTRACT
Leakage power is one of the most critical issues for ultra-deep submicron technology. Subthreshold leakage depends exponentially on linewidth, and consequently variation in linewidth translates to a large leakage variation. A significant fraction of variation in linewidth occurs due to systematic variations involving focus and pitch. In this paper we propose a new leakage estimation methodology that accounts for focus-dependent variation in linewidth. The ideas presented in this paper significantly improve leakage estimation and can be used in existing leakage reduction techniques to improve their efficacy. We modify the previously proposed gate length biasing technique of [9] to consider systematic variations in linewidth and further reduce leakage power. Our method reduces the leakage spread between worst and best process corners by up to 62%. Defocus awareness improves leakage reduction from gate length biasing by up to 7%
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Berkeley predictive technology model. http://www-device.eecs.berkeley.edu/~ptm.
|
 |
2
|
Amit Agarwal , Chris H. Kim , Saibal Mukhopadhyay , Kaushik Roy, Leakage in nano-scale technologies: mechanisms, impact and design considerations, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996571]
|
 |
3
|
Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.775920]
|
| |
4
|
Y. Cao, T. Sato, M. Orshansky, D. Sylvester and C. Hu. New Paradigm of Predictive MOSFET and Interconnect Modeling for Early circuit Design. In Proc. Custom Integrated Circuits Conference, pp. 201--204, 2000.
|
| |
5
|
R. Choudhury. Handbook of Microlithography and Micromachining Volume:1. In SPIE Press Monograph, 2002.
|
| |
6
|
J. Fishburn and A. Dunlop. Tilos: A posynomial programming approach to transistor-sizing. In Proc. IEEE Intl. Conf. on Computer Aided Design, pp. 326--328, 1985.
|
| |
7
|
D. G. Flagello, H. van der Laan, J. van Schoot, I. Bouchoms and B. Geh. Understanding systematic and random cd variations using predictive modelling techniques. In SPIE Conf. Optical Microlithography XII, pp. 162--175, 1999.
|
 |
8
|
|
 |
9
|
Puneet Gupta , Andrew B. Kahng , Puneet Sharma , Dennis Sylvester, Selective gate-length biasing for cost-effective runtime leakage control, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996661]
|
| |
10
|
|
| |
11
|
B. Lee. Modeling of Chemical Mechanical Polishing for Shallow Trench Isolation. PhD thesis, Massachusetts Institute of Technology, 2002.
|
| |
12
|
D. O. Ouma, D. S. Boning, J. E. Chung, W. G. Easter, V. Saxena, S. Misra and A. Crevasse. Characterization and Modeling of Oxide Chemical Mechanical Polishing Using Planarization Length and Pattern Density. In IEEE Tran. on Semiconductor Manufacturing, Vol. 15(2), pp. 232--244, 2002.
|
 |
13
|
|
| |
14
|
|
|