Article

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation

Authors:

Margaret Martonosi,

Sharad MalikAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 287 - 292

https://doi.org/10.1145/1077603.1077670

Published: 08 August 2005 Publication History

Abstract

Dynamic voltage/frequency scaling (DVFS) has been shown to be an efficient power/energy reduction technique. Various runtime DVFS policies have been proposed to utilize runtime DVFS opportunities. However, it is hard to know if runtime DVFS opportunities have been fully exploited by a DVFS policy without knowing the upper bounds of possible energy savings. We propose an exact but exponential algorithm to determine the upper bound of energy savings. The algorithm takes into consideration the switching costs, discrete voltage/frequency voltage levels and different program states. We then show a fast linear time heuristic can provide a very close approximate to this bound

References

[1]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture, June 2000.]]

Digital Library

[2]

T. Burd and R. Brodersen. Design issues for dynamic voltage scaling. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED-00), June 2000.]]

Digital Library

[3]

D. Burger, T. M. Austin, and S. Bennett. Evaluating future microprocessors: the SimpleScalar tool set. Tech. Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept., July 1996.]]

[4]

K. Choi, R. Soma, and M. Pedram. Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. pages 18--28, Jan 2005.]]

Digital Library

[5]

L. Clark. Circuit Design of XScale (tm) Microprocessors, 2001. In 2001 Symposium on VLSI Circuits, Short Course on Physical Design for Low-Power and High-Performance Microprocessor Circuits.]]

[6]

Intel Corp. Intel XScale (tm) Core Developer's Manual, 2003. http://developer.intel.com/design/intelxscale/.]]

[7]

T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In International Symposium on Low Power Electronics and Design (ISLPED-98), pages 197--202, August 1998.]]

Digital Library

[8]

R. Jejurikar and R. Gupta. Energy aware task scheduling with task synchronization for embedded real time systems. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 164--169, 2002.]]

Digital Library

[9]

C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communication Systems. In Proceedings of the 30th International Symp. on Microarchitecture, Dec. 1997.]]

Digital Library

[10]

J. Lorch and A. Smith. Improving dynamic voltage algorithms with PACE. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2001), June 2001.]]

Digital Library

[11]

P. Pillai and K. G. Shin. Real-time dynamic voltage scaling for low-power embedded operating systems. In Proceedings of the 18th ACM Symp. on Operating Systems Principles, 2001.]]

Digital Library

[12]

G. Qu. What is the limit of energy saving by dynamic voltage scaling? In Proceedings of the International Conference on Computer Aided Design, 2001.]]

Digital Library

[13]

A. Sinha and A. Chandrakasan. Dynamic voltage scheduling using adpative filtering of workload traces. In Proceedings of the 14th International Conference on VLSI Design, Jan 2001.]]

Digital Library

[14]

Transmeta Corporation. Crusoe processor documentation, 2002. http://www.transmeta.com.]]

[15]

M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced CPU energy. In the 1st Symposuim on Operating Systems Design and Implementation (OSDI-94), pages 13--23, 1994.]]

Digital Library

[16]

A. Weissel and F. Bellosa. Process cruise control: event-driven clock scaling for dynamic power management. In CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, pages 238--246, 2002.]]

Digital Library

[17]

F. Xie, M. Martonosi, and S. Malik. Compile-time dynamic voltage scaling settings: Opportunities and limits. In Proceedings of ACM SIGPLAN Conference on Programming Languages, Design, and Implementation (PLDI'03), June 2003.]]

Digital Library

[18]

F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced CPU energy. In Proceedings of the 36th Annual Symposium on Foundations of Computer Science (FOCS'95), page 374. IEEE Computer Society, 1995.]]

Digital Library

Cited By

Rani RGarg R(2021)A Survey of Thermal Management in Cloud Data Centre: Techniques and Open IssuesWireless Personal Communications10.1007/s11277-020-08039-xOnline publication date: 15-Jan-2021
https://doi.org/10.1007/s11277-020-08039-x
Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Chakraborty SKapoor H(2018)Analysing the Role of Last Level Caches in Controlling Chip TemperatureIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28235423:4(289-305)Online publication date: 1-Oct-2018
https://doi.org/10.1109/TSUSC.2018.2823542
Show More Cited By

Index Terms

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Model verification and validation

Recommendations

The limit of dynamic voltage scaling and insomniac dynamic voltage scaling

Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum V_dd. However, there is no fundamental reason why ...
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling

Dynamic voltage scaling (DVS) has become an important dynamic power-management technique to save energy. DVS tunes the power-performance tradeoff to the needs of the application. The goal is to minimize energy consumption while meeting performance ...
Analysis of energy reduction on dynamic voltage scaling-enabled systems

Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency, based on the computation load, to provide the desired performance with the minimal amount of energy consumption. It has been demonstrated as one of the most ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 August 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISLPED05

Sponsor:

ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

32
Total Citations
View Citations
394
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 07 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Rani RGarg R(2021)A Survey of Thermal Management in Cloud Data Centre: Techniques and Open IssuesWireless Personal Communications10.1007/s11277-020-08039-xOnline publication date: 15-Jan-2021
https://doi.org/10.1007/s11277-020-08039-x
Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Chakraborty SKapoor H(2018)Analysing the Role of Last Level Caches in Controlling Chip TemperatureIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28235423:4(289-305)Online publication date: 1-Oct-2018
https://doi.org/10.1109/TSUSC.2018.2823542
Medhat RFunk SRountree B(2017)Scalable performance bounding under multiple constrained renewable resourcesProceedings of the 5th International Workshop on Energy Efficient Supercomputing10.1145/3149412.3149422(1-8)Online publication date: 12-Nov-2017
https://dl.acm.org/doi/10.1145/3149412.3149422
Wang RShang PZhang JWang QLiu TWang J(2016)MAR: A Novel Power Management for CMP Systems in Data-Intensive EnvironmentIEEE Transactions on Computers10.1109/TC.2015.245885465:6(1816-1830)Online publication date: 1-Jun-2016
https://doi.org/10.1109/TC.2015.2458854
Lukefahr APadmanabha SDas RDreslinski RWenisch TMahlke SAmaral JTorrellas J(2014)Heterogeneous microarchitectures trump voltage scaling for low-power coresProceedings of the 23rd international conference on Parallel architectures and compilation10.1145/2628071.2628078(237-250)Online publication date: 24-Aug-2014
https://dl.acm.org/doi/10.1145/2628071.2628078
Meisner DWenisch T(2012)DreamWeaverACM SIGPLAN Notices10.1145/2248487.215100947:4(313-324)Online publication date: 3-Mar-2012
https://dl.acm.org/doi/10.1145/2248487.2151009
Meisner DWenisch T(2012)DreamWeaverACM SIGARCH Computer Architecture News10.1145/2189750.215100940:1(313-324)Online publication date: 3-Mar-2012
https://dl.acm.org/doi/10.1145/2189750.2151009
Meisner DWenisch THarris TScott M(2012)DreamWeaverProceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems10.1145/2150976.2151009(313-324)Online publication date: 3-Mar-2012
https://dl.acm.org/doi/10.1145/2150976.2151009
Qin XWang WMishra P(2012)TCECIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.219082431:8(1159-1168)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2190824
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten