ACM Home Page
Please provide us with feedback. Feedback
Energy reduction in multiprocessor systems using transactional memory
Full text PdfPdf (106 KB)
Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2005 international symposium on Low power electronics and design table of contents
San Diego, CA, USA
POSTER SESSION: I/O and memory system design table of contents
Pages: 331 - 334  
Year of Publication: 2005
ISBN:1-59593-137-6
Authors
Tali Moreshet  Brown University, Providence, RI
R. Iris Bahar  Brown University, Providence, RI
Maurice Herlihy  Brown University, Providence, RI
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 59,   Citation Count: 1
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1077603.1077683
What is a DOI?

ABSTRACT

The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniprocessors. In this work we focus on new energy consumption issues unique to multiprocessor systems: synchronization of accesses to shared memory. We investigate and compare different means of providing atomic access to shared memory, including locks and lock-free synchronization (i.e., transactional memory), with respect to energy as well as performance. We show that transactional memory has an advantage in terms of energy consumption over locks, but that this advantage largely depends on the system architecture, the contention level, and the policy of conflict resolution


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
3
 
4
M. Ekman and P. Stenstr¨ om. Performance and power impact of issue-width in chip-multiprocessor cores. In ICPP, October 2003.
5
6
7
8
 
9
J. W. Janzen. SDRAM Power Calculation Sheet. Micron, 2001.
 
10
 
11
12
13
14
 
15
 
16
P. Shivakumar and N. P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model. Technical report, Compaq Western Research Laboratory, 2001/2.
17
 
18
 
19
Virtutech. Simics. https://www.simics.net.


Collaborative Colleagues:
Tali Moreshet: colleagues
R. Iris Bahar: colleagues
Maurice Herlihy: colleagues