Article

System level power and performance modeling of GALS point-to-point communication interfaces

Authors:

Koushik Niyogi,

Diana MarculescuAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 381 - 386

https://doi.org/10.1145/1077603.1077694

Published: 08 August 2005 Publication History

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Abstract

Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising technique in the system on a chip (SoC) era. In the context of today's increasingly complex SoCs, there is a need for design methodologies that start at higher levels of abstraction. Much of the previous work has been devoted to design of asynchronous communication schemes such as mixed clock FIFOs and pausible clocks for globally asynchronous, locally synchronous systems, but at low levels of abstraction, such as circuit level. To enable early design evaluation of such schemes, this paper proposes to use a SystemC-based modeling methodology for the asynchronous communication among various locally synchronous islands. The modeling framework encompasses various levels of abstraction and enables system-level validation of circuit or RT level hardware descriptions, as well as their impact on high-level design decisions

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Cited By

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Xiang DPan Q(2019)Low-power and high-performance adaptive routing in on-chip networksCCF Transactions on High Performance Computing10.1007/s42514-019-00009-5Online publication date: 2-Jul-2019
https://doi.org/10.1007/s42514-019-00009-5
Lussari EOliveira DFaria LVerducci Ode Lima Monteiro DTorres FIndrusiak L(2016)Software-defined radio design based on GALS architecture for FPGAsProceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains10.5555/3145862.3145902(1-6)Online publication date: 29-Aug-2016
https://dl.acm.org/doi/10.5555/3145862.3145902
Lussari EOliveira DFaria LVerducci O(2016)Software-Defined Radio design based on GALS architecture for FPGAs2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2016.7724076(1-6)Online publication date: Aug-2016
https://doi.org/10.1109/SBCCI.2016.7724076
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Index Terms

System level power and performance modeling of GALS point-to-point communication interfaces
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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Published In

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Xiang DPan Q(2019)Low-power and high-performance adaptive routing in on-chip networksCCF Transactions on High Performance Computing10.1007/s42514-019-00009-5Online publication date: 2-Jul-2019
https://doi.org/10.1007/s42514-019-00009-5
Lussari EOliveira DFaria LVerducci Ode Lima Monteiro DTorres FIndrusiak L(2016)Software-defined radio design based on GALS architecture for FPGAsProceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains10.5555/3145862.3145902(1-6)Online publication date: 29-Aug-2016
https://dl.acm.org/doi/10.5555/3145862.3145902
Lussari EOliveira DFaria LVerducci O(2016)Software-Defined Radio design based on GALS architecture for FPGAs2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2016.7724076(1-6)Online publication date: Aug-2016
https://doi.org/10.1109/SBCCI.2016.7724076
Garg SMarculescu D(2013)Mitigating the Impact of Process Variation on the Performance of 3-D Integrated CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.222676221:10(1903-1914)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2226762
Truong DBaas BSapatnekar S(2010)Circuit modeling for practical many-core architecture design explorationProceedings of the 47th Design Automation Conference10.1145/1837274.1837432(627-628)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837432
Garg SMarculescu DBenini LDe Micheli GAl-Hashimi BMueller W(2009)System-level process variability analysis and mitigation for 3D MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874772(604-609)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874772
Kahng ALi BPeh LSamadi KBenini LDe Micheli GAl-Hashimi BMueller W(2009)ORION 2.0Proceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874721(423-428)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874721
Salimi Khaligh RRadetzki M(2009)Adaptive Interconnect Models for Transaction-Level SimulationLanguages for Embedded Systems and their Applications10.1007/978-1-4020-9714-0_10(149-165)Online publication date: 2009
https://doi.org/10.1007/978-1-4020-9714-0_10
Garg SMarculescu D(2008)System-level throughput analysis for process variation aware multiple voltage-frequency island designsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139196713:4(1-25)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391967
Goldstein S(2005)The impact of the nanoscale on computing systemsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129695(655-661)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129695
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Abstract

References

Cited By

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Recommendations

Two efficient synchronous ↔ asynchronous converters well-suited for networks-on-chip in GALS architectures

Point to Point GALS Interconnect

From synchronous to GALS: A new architecture for FPGAs

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