An algorithm for integrated pin assignment and buffer planning
Abstract
References
Index Terms
- An algorithm for integrated pin assignment and buffer planning
Recommendations
An algorithm for integrated pin assignment and buffer planning
DAC '02: Proceedings of the 39th annual Design Automation ConferenceThe buffer block methodology has become increasingly popular as more and more buffers are needed in deep-submicron design, and it leads to many challenging problems in physical design. In this paper, we present a polynomial-time exact algorithm for ...
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs
Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs ...
Ordered escape routing via routability-driven pin assignment
GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSIFor board-level routing, ordered escape routing is a key problem. In this paper, based on the optimality of hierarchical bubble sorting, the process of assigning routability-driven pins is done for single-layer routing. Furthermore, an efficient routing ...
Comments
Information & Contributors
Information
Published In
![cover image ACM Transactions on Design Automation of Electronic Systems](/cms/asset/a3aa0045-c94b-499c-baee-65e286141e99/default_cover.png)
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Check for updates
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 362Total Downloads
- Downloads (Last 12 months)2
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in