Design of a decompressor engine on a SPARC processor

ABSTRACT

Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumption, due to an increase in the cache hit ratio. This paper proposes the design of a code decompressor engine for our dictionary-based method, embedding it into the Leon (SPARC V8) processor. Our design guarantees that the processor cycle-time is maintained and the decompression is performed on-the-fly. We have achieved a functional implementation on a FPGA, with compression ratios ranging from 72% to 88%, performance improvement as high as 45% and a reduction on energy consumption reaching 35%, validated through two real-world benchmarks suites: MediaBench and MiBench. We also explore some trade-offs between compression ratio and performance.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Design, Performance

Keywords:
code compression, performance