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Total leakage power optimization with improved mixed gates

Published: 04 September 2005 Publication History

Abstract

Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness of gate oxide layer Tox. In this paper, we propose a new method that combines approaches of Dual Threshold CMOS (DTCMOS), mixed-Tox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant.

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  • (2014)Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865491(1740-1743)Online publication date: Jun-2014
  • (2012)Graph modeling for Static Timing Analysis at transistor level in nano-scale CMOS circuits2012 16th IEEE Mediterranean Electrotechnical Conference10.1109/MELCON.2012.6196385(80-83)Online publication date: Mar-2012
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    cover image ACM Conferences
    SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design
    September 2005
    271 pages
    ISBN:1595931740
    DOI:10.1145/1081081
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 September 2005

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    Author Tags

    1. MVT
    2. leakage currents
    3. threshold voltage

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    SBCCI05: 18th Symposium on Integrated Circuits and System Design
    September 4 - 7, 2005
    Florianolpolis, Brazil

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    Overall Acceptance Rate 133 of 347 submissions, 38%

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    View all
    • (2019)Enhancing the Design of Body Built-In Sensor ArchitecturesOn-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits10.1007/978-3-030-29353-6_4(55-77)Online publication date: 1-Oct-2019
    • (2014)Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865491(1740-1743)Online publication date: Jun-2014
    • (2012)Graph modeling for Static Timing Analysis at transistor level in nano-scale CMOS circuits2012 16th IEEE Mediterranean Electrotechnical Conference10.1109/MELCON.2012.6196385(80-83)Online publication date: Mar-2012
    • (2011)Efficient multi‐threshold voltage techniques for minimum leakage current in nanoscale technologyInternational Journal of Circuit Theory and Applications10.1002/cta.68639:10(1049-1066)Online publication date: 17-Oct-2011
    • (2007)High-speed, low-leakage integrated circuitsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.10.00153:5-6(321-327)Online publication date: 1-May-2007
    • (2006)Biologically-Inspired optimization of circuit performance and leakageProceedings of the 19th international conference on Architecture of Computing Systems10.1007/11682127_25(352-366)Online publication date: 13-Mar-2006
    • (2005)Total leakage reduction by observance of parameter variations2005 NORCHIP10.1109/NORCHP.2005.1597039(261-264)Online publication date: 2005

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