Article

Efficient behavior-driven runtime dynamic voltage scaling policies

Authors:

Margaret Martonosi,

Sharad MalikAuthors Info & Claims

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 105 - 110

https://doi.org/10.1145/1084834.1084864

Published: 19 September 2005 Publication History

Abstract

Power consumption has long been a limiting factor in microprocessor design. In seeking energy efficiency solutions, dynamic voltage/frequency scaling (DVFS), a technique to vary voltage/frequency on the fly, has emerged as a powerful and practical power/energy reduction technique that exploits computation slack due to relaxed deadlines and memory accesses. DVFS has been implemented in some modern processors such as Intel XScale and Transmeta Crusoe. Hence the bulk of research efforts have been devoted to developing policies to detect slack and pick appropriate V/f assignments such that the energy is minimized while meeting performance requirements. Since slack is a product of memory accesses and relaxed deadlines, the number of instances and the duration of available slack are highly dependent on the runtime program behavior. Runtime DVFS policies must take into consideration program characteristics in order to achieve significant energy savings. In this paper, we characterize program behavior and classify programs in terms of the memory access behavior. We propose a runtime DVFS policy that takes into consideration the characteristics of program behavior for each category. Then we examine the efficiency of the proposed DVFS policies by comparing with previously derived upper bounds of energy savings. Results show that the proposed runtime DVFS policies approach the upper bounds of energy savings in most cases.

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Cited By

Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Vougioukas ISandberg ADiestelhorst SAl-Hashimi BMerrett G(2017)NucleusACM Transactions on Embedded Computing Systems10.1145/312654416:5s(1-16)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126544
De Sensi DTorquati MDanelutto M(2016)A Reconfiguration Algorithm for Power-Aware Parallel ApplicationsACM Transactions on Architecture and Code Optimization10.1145/300405413:4(1-25)Online publication date: 2-Dec-2016
https://dl.acm.org/doi/10.1145/3004054
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Index Terms

Efficient behavior-driven runtime dynamic voltage scaling policies
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
2. Software and its engineering
  1. Software organization and properties
    1. Software system structures
      1. Embedded software
      2. Real-time systems software

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cover image ACM Conferences

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2005

356 pages

ISBN:1595931619

DOI:10.1145/1084834

General Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden
,
Program Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 September 2005

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CODES/ISSS05

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CODES/ISSS05: Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 19 - 21, 2005

NJ, Jersey City, USA

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CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Vougioukas ISandberg ADiestelhorst SAl-Hashimi BMerrett G(2017)NucleusACM Transactions on Embedded Computing Systems10.1145/312654416:5s(1-16)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126544
De Sensi DTorquati MDanelutto M(2016)A Reconfiguration Algorithm for Power-Aware Parallel ApplicationsACM Transactions on Architecture and Code Optimization10.1145/300405413:4(1-25)Online publication date: 2-Dec-2016
https://dl.acm.org/doi/10.1145/3004054
Nath RTullsen DPrvulovic M(2015)The CRISP performance model for dynamic voltage and frequency scaling in a GPGPUProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830826(281-293)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830826
Lukefahr APadmanabha SDas RDreslinski RWenisch TMahlke SAmaral JTorrellas J(2014)Heterogeneous microarchitectures trump voltage scaling for low-power coresProceedings of the 23rd international conference on Parallel architectures and compilation10.1145/2628071.2628078(237-250)Online publication date: 24-Aug-2014
https://dl.acm.org/doi/10.1145/2628071.2628078
Chandra SRaghunathan ADey S(2012)Variation-aware voltage level selectionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.212605020:5(925-936)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2126050
Eyerman SEeckhout L(2011)Fine-grained DVFS using on-chip regulatorsACM Transactions on Architecture and Code Optimization10.1145/1952998.19529998:1(1-24)Online publication date: 5-Feb-2011
https://dl.acm.org/doi/10.1145/1952998.1952999
Eyerman SEeckhout L(2010)A Counter Architecture for Online DVFS Profitability EstimationIEEE Transactions on Computers10.1109/TC.2010.6559:11(1576-1583)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TC.2010.65
Ghodrat MGivargis TRosenstiel WWakabayashi K(2009)Efficient dynamic voltage/frequency scaling through algorithmic loop transformationProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629464(203-210)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629464
Chang MTseng SLin HSu C(2009)Implementation and Optimization of DSP Suspend Resume on Dual-Core SOCProceedings of the 2009 International Conference on Embedded Software and Systems10.1109/ICESS.2009.52(185-190)Online publication date: 25-May-2009
https://dl.acm.org/doi/10.1109/ICESS.2009.52
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