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Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines

Published: 19 September 2005 Publication History

Abstract

The performance of virtual machines (e.g., Java Virtual Machines---JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a Java Virtual Machine platform, making it capable of accelerating any Java bytecode method by using platform-independent hardware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer.

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Cited By

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  • (2009)Dynamically utilizing computation accelerators for extensible processors in a software approachProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629443(51-60)Online publication date: 11-Oct-2009
  • (2009)From Silicon to ScienceACM Transactions on Reconfigurable Technology and Systems10.1145/1575779.15757862:4(1-15)Online publication date: 1-Sep-2009

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  1. Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines

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    cover image ACM Conferences
    CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
    September 2005
    356 pages
    ISBN:1595931619
    DOI:10.1145/1084834
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 19 September 2005

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    Author Tags

    1. accelerator
    2. synthesis
    3. virtual machine

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    CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;
    Overall Acceptance Rate 280 of 864 submissions, 32%

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    • (2009)Dynamically utilizing computation accelerators for extensible processors in a software approachProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629443(51-60)Online publication date: 11-Oct-2009
    • (2009)From Silicon to ScienceACM Transactions on Reconfigurable Technology and Systems10.1145/1575779.15757862:4(1-15)Online publication date: 1-Sep-2009

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