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Exploiting pipelining to relax register-file port constraints of instruction-set extensions

Published: 24 September 2005 Publication History

Abstract

Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). While these processors have become available, the state of the art on automatic ISE identification is improving; many algorithms are being proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the microarchitecture---some processors indeed only allow two read and one write ports---and, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. This paper proposes a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint [1, 16, 4, 19] and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. This paper proposes an algorithm for scheduling graphs---corresponding to ISEs---under input/output constraint; experiments show that by using the proposed method applications can be sped-up tangibly: speedup for low I/O constraints is 32% better on average, and 65% better at best, than that obtained by state of the art techniques.

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  1. Exploiting pipelining to relax register-file port constraints of instruction-set extensions

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      cover image ACM Conferences
      CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
      September 2005
      326 pages
      ISBN:159593149X
      DOI:10.1145/1086297
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      Published: 24 September 2005

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      Author Tags

      1. automatic instruction-set extension
      2. constrained scheduling
      3. embedded customised architectures
      4. input/output
      5. multi-cycle register access

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      • (2024)Automating application-driven customization of ASIPs: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103080148(103080)Online publication date: Mar-2024
      • (2020)GNSS-ISE: Instruction Set Extension for GNSS Baseband ProcessingSensors10.3390/s2002046520:2(465)Online publication date: 14-Jan-2020
      • (2019)RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source CodeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281868938:4(741-754)Online publication date: Apr-2019
      • (2017)Generating ASIPs with Reduced Number of Connections to the Register-FileInternational Journal of Parallel Programming10.1007/s10766-017-0491-445:6(1461-1487)Online publication date: 1-Dec-2017
      • (2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_13-1(1-33)Online publication date: 8-Apr-2017
      • (2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_13(377-409)Online publication date: 27-Sep-2017
      • (2016)Instruction set extensions for secure applicationsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972165(1529-1534)Online publication date: 14-Mar-2016
      • (2015)Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom InstructionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.238737534:3(483-494)Online publication date: Mar-2015
      • (2015)Generating ASIPs with reduced number of connections to the register-file2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)10.1109/SAMOS.2015.7363681(238-245)Online publication date: Jul-2015
      • (2014)Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible StorageACM Transactions on Architecture and Code Optimization10.1145/257687711:2(1-26)Online publication date: 15-Jul-2014
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