DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency

ABSTRACT

The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory latency on the interconnection network. It can be applied at a same implementation cost as traditional bi-directional ring systems. We compare the performance of the proposed system to that of the traditional bi-directional ring-based system and toroidal mesh-based system. By simulations, it is shown that the proposed system outperforms the traditional bi-directional ring-based system by 42~101 % and excels the toroidal mesh-based system by 4~14%.

REFERENCES

• 1: R. Rabenseifner, "Hybrid Parallel Programming on HPC Platforms", Proc. Fifth European Workshop on OpenMP. (EWOMP-03), Sept. 22--26, 2003, pp 185--194.
• 2: L. Smith and M. Bull, "Development of mixed mode MPI / OpenMP applications", Scientific Programming, vol. 9, no. 2-3, 2001, pp. 83--98.
• 3: R. Kutil and A. Uhl. "Architecture comparison in a high bandwidth application", Proc. Int'l Workshop on Parallel Numerics. (PARNUM-2000), Sept. 2000, pp. 219--228.
• 4: IEEE Computer Society, IEEE Standard for Scalable Coherent Interface(SCI), Inst. of Electrical and Electronics Engineers, Aug. 1993.
• 5: J. Tao, W. Karl, and M. Schulz, "A novel approach for data distribution on NUMA machines", Proc. Int'l Conf. Architecture of Computing Systems. (ARCS-02), Apr. 2002, pp. 189--195.
• 6: Hitoshi Oi and N. Ranganathan, "A Comparative Study of Bidirectional Ring and Crossbar Interconnection Networks", Proc. Int'l Conf. Parallel and Distributed Processing Techniques and Applications. (PDPTA-98), July 1998, pp 883--890.
• 7: Data General AViiON, http://www.dg.com.
• 8: Byoung Soon Jang , Sung Woo Chung , Seong Tae Jhang , Chu Shik Jhon, Efficient schemes to scale the interconnection network bandwidth in a ring-based multiprocessor system, Proceedings of the 2001 ACM symposium on Applied computing, p.510-516, March 2001, Las Vegas, Nevada, United States [doi>10.1145/372202.372447]
• 9: Michael Dubois , Luiz André Barroso, Performance Evaluation of the Slotted Ring Multiprocessor, IEEE Transactions on Computers, v.44 n.7, p.878-890, July 1995 [doi>10.1109/12.392846 ]
• 10: Anthony-Trung Nguyen , Maged Michael , Arun Sharma , Josep Torrella, The Augmint multiprocessor simulation toolkit for Intel x86 architectures, Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors, p.486, October 07-09, 1996
• 11: Steven Cameron Woo , Moriyoshi Ohara , Evan Torrie , Jaswinder Pal Singh , Anoop Gupta, The SPLASH-2 programs: characterization and methodological considerations, Proceedings of the 22nd annual international symposium on Computer architecture, p.24-36, June 22-24, 1995, S. Margherita Ligure, Italy

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

General Terms:
Performance, Theory