SH-X: an embedded processor core for consumer appliances

ABSTRACT

A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100, μA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.

REFERENCES

• 1: T. Yamada et al., "A 133MHz 170mW 10μA Standby Application Processor for 3G Cellular Phones," ISSCC Dig. Tech. Papers, pp. 370--371, 474, Feb. 2002.
• 2: T. Yamada et al., "A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications," IEICE Transactions, Vol. E85-C No. 2, pp. 253--262, Feb. 2002.
• 3: T. Tsunoda et al., "Application Processor for 3G Cellular Phones," COOL Chips V Proceedings, Vol. I, pp. 102--111, April 2002.
• 4: K. Kutaragi et al., "A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," ISSCC Dig. Tech. Papers, pp. 256--257, Feb. 1999.
• 5: R. Rogenmoser et al., "A Dual-Issue Floating-Point Coprocessor with SIMD Architecture and Fast 3D Functions," ISSCC Dig. Tech. Papers, pp. 414--415, Feb. 2002.
• 6: F. Arakawa et al., "SH4 RISC Multimedia Microprocessor" HOT Chips IX Symposium Record, pp. 165--176, Aug. 1997.
• 7: O. Nishii et al., "A 200MHz 1.2W 1.4GFLOPS microprocessor with graphic operation unit," ISSCC Dig. Tech. Papers, Feb. 1998, pp. 288--289, 447.
• 8: Fumio Arakawa , Osamu Nishii , Kunio Uchiyama , Norio Nakagawa, SH4 RISC Multimedia Microprocessor, IEEE Micro, v.18 n.2, p.26-34, March 1998 [doi>10.1109/40.671400 ]
• 9: F. Arakawa et al., "An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36M Polygons/s FPU," ISSCC Dig. Tech. Papers, pp. 334--335, 531, Feb. 2004.
• 10: T. Kamei et al., "A Resume-Standby Application Processor for 3G Cellular Phones," ISSCC Dig. Tech. Papers, pp. 336--337, 531, Feb. 2004.
• 11: S. Yoshioka and T. Hattori, "SH-X 4500MIPS/W 2 2-Way Superscalar CPU Core and its SoC Products," Microprocessor Forum 2003 Conference Program, Session 4: Low-Power Processors, San Jose, USA, Oct. 2003.
• 12: Y. Kanno et al., "μI/O Architecture for 0.13 μm Wide-Voltage-Range System-on-a-Package (SOP) Designs," Dig. Symp. VLSI Circuits, pp. 168--169, 2002.
• 13: M. Yamaoka et al., "A 300MHz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor" ISSCC Dig. Tech. Papers, pp. 494--495, 542, Feb. 2004.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Pipeline processors

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures
          Subjects: Mobile processors
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Design, Performance, Theory