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ABSTRACT
Often reconfigurable systems are reported to have 10× to 100× speedup over that of a software system. However, the reconfigurable hardware must usually be combined with software to form an entire system. This system integration presents a hardware/software co-design problem with many system engineering issues. Here, we present traffic acceleration on the Cray XD1 supercomputer and describe the costs involved in different hardware/software trade-offs.
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Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 5
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Akila Gothandaraman , Gregory D. Peterson , G. L. Warren , Robert J. Hinde , Robert J. Harrison, FPGA acceleration of a quantum Monte Carlo application, Parallel Computing, v.34 n.4-5, p.278-291, May, 2008
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