Article

Fast simulation of VLSI interconnects

Authors:

J. Jain,

Cheng-Kok Koh,

V. BalakrishnanAuthors Info & Claims

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Pages 93 - 98

https://doi.org/10.1109/ICCAD.2004.1382549

Published: 07 November 2004 Publication History

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Abstract

This work introduces an efficient and accurate interconnect simulation technique. A new formulation for typical VLSI interconnect structures is proposed which, in addition to providing a compact set of modeling equations, also offers a potential for exploiting sparsity at the simulation level. Simulations show that our approach can achieve 50 /spl times/ improvement in computation time and memory over INDUCTWISE (which in turn has been shown to be 400 /spl times/ faster than SPICE) while preserving simulation accuracy.

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Cited By

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(2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
Tanji YWatanabe TKubota HAsai HGielen G(2006)Large scale RLC circuit analysis using RLCG-MNA formulationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131495(45-46)Online publication date: 6-Mar-2006
Yang YKoh CBalakrishnan VHirose F(2006)Adaptive admittance-based conductor meshing for interconnect analysisProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118423(509-514)Online publication date: 24-Jan-2006
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Fast simulation of VLSI interconnects
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Published In

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

November 2004

913 pages

ISBN:0780387023

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IEEE Computer Society

United States

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Published: 07 November 2004

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ICCAD04

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SIGDA

ICCAD04: The International Conference on Computer-Aided Design 2004

November 7 - 11, 2004

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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(2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
Tanji YWatanabe TKubota HAsai HGielen G(2006)Large scale RLC circuit analysis using RLCG-MNA formulationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131495(45-46)Online publication date: 6-Mar-2006
Yang YKoh CBalakrishnan VHirose F(2006)Adaptive admittance-based conductor meshing for interconnect analysisProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118423(509-514)Online publication date: 24-Jan-2006
Jain JCauley SKoh CBalakrishnan VHirose F(2006)SASIMIProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118402(422-427)Online publication date: 24-Jan-2006
Lam WJain JKoh CBalakrishnan VChen Y(2005)Statistical based link insertion for robust clock network designProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129684(588-591)Online publication date: 31-May-2005

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A fast simulation approach for inductive effects of VLSI interconnects

An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation

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