A quantitative study and estimation models for extensible instructions in embedded processors

ABSTRACT

Designing extensible instructions is a computationally complex task, due to the large design space each instruction is exposed to. One method of speeding up the design cycle is to characterize instructions and estimate their peculiarities during a design exploration. In this paper, we study and derive three estimation models for extensible instructions: area overhead, latency, and power consumption under a wide range of customization parameters. System decomposition and regression analysis are used as the underlying methods to characterize and analyze extensible instructions. We verify our estimation models using automatically and manually generated extensible instructions, plus extensible instructions used in large real-world applications. The mean absolute error of our estimation models arc as small as: 3.4% (6.7% max.) for area overhead, 5.9% (9.4% max.) for latency, and 4.2% (7.2% max.) for power consumption, compared to estimation through the time consuming synthesis and simulation steps using commercial tools. Our estimation models achieve an average speedup of three orders of magnitude over the commercial tools and thus enable us to conduct a fast and extensive design space exploration that would otherwise not be possible. The estimation models are integrated into our extensible processor tool suite.

References

1. {1} S. Aditya, B. R. Rau, and V. Kathail, "Automatic architectural synthesis of vliw and epic processors," in ISSS, 1999.
2. {2} A. Peymandoust, L. Pozzi, P. Ienne, and G. Micheli, "Automatic instruction-set extension and utilization for embedded processors," in ASAP, 2003.
3. {3} H. Zima and B. Chapman, "Supercompilers for parallel and vector computers," in Addison-Wesley (ACM), 1990.
4. {4} Y. Wand and R. Weber, "An ontological model of an information system," in IEEE Tran. of Software Engineering, 1990.
5. {5} "Splus." Insightful, Inc. (http://www.insightful.com).
6. {6} J. Henkel, "Closing the soc design gap," in IEEE Computer Magazine, vol. 36, Iss. 9, pp. 119-121., 2003.
7. {7} K. Keutzer, S. Malik, and A. R. Newton, "From asic to asip: The next design discontinuity," in ICCD, 2002.
8. {8} "Arctangent processor." ARC, Inc. (http://www.arc.com).
9. {9} "Asip-meister." (http://www.eda-meister.org/asip-meister/).
10. {10} "Jazz dsp." Improv Systems, Inc. (http://www.improvsys.com).
11. {11} "Lisatek." CoWare, Inc. (http://www.coware.com).
12. {12} "Xtensa processor." Tensilica, Inc. (http://www.tensilica.com).
13. {13} H. Choi, J.-S. Kim, C. W. Yoon, et al., "Synthesis of application specific instructions for embedded dsp software," in IEEE Trans. Computers, 1999.
14. {14} V. Kathail, S. Aditya, R. Schreiber, B. R. Rau, D. C. Cron-quist, and M. Sivaraman, "Pico: Automatically designing custom computers," in Computer, 2002.
15. {15} J. Lee, K. Choi, and N. Dutt, "Efficient instruction encoding for automatic instruction set design of configurable asips," in ICCAD, 2002.
16. {16} K. Atasu, L. Pozzi, and P. Lenne, "Automatic application-specific instruction-set extensions under microarchitectural constraints," in DAC, 2003.
17. {17} F. Sun, A. Raghunathan, S. Ravi, and N. K. Jha, "A scalable application specific processor synthesis methodology," in ICCAD, 2003.
18. {18} N. Clark, W. Tang, and S. Mahlke, "Automatically generating custom instruction set extensions," in WASP, 2002.
19. {19} P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh, "Instruction generation and regularity extraction for reconfigurable processors," in CASES, 2002.
20. {20} D. Goodwin and D. Petkov, "Automatically generating custom instruction set extensions," in CASES, 2003.
21. {21} J. Sanghavi and A. Wang, "Estimation of speed, area, and power of parameterizable soft ip," in DAC, 2001.
22. {22} A. Bona, M, Sami, D. Soluto, C. Silvano, V. Zaccaria, and R. Zafalon, "Energy estimation and optimization of embedded vliw processors based on instruction clustering," in DAC, 2002.
23. {23} Y. Fei, S. Ravi, A. Raghunathan, and N. Jha, "Energy estimation for extensible processors," in DATE, 2003.
24. {24} N. Cheung, J. Henkel, and S. Parameswaran, "Rapid configuration & instruction selection for an asip: A case study," in DATE, 2003.
25. {25} P. Jha and N. Dutt, "Rapid estimation for parameterized components in high-level synthesis," in IEEE Tran. on VLSI, 1993.
26. {26} "Design compiler." Synopsys, Inc. (http://www.synopsys.com).
27. {27} "Powertheater." Sequence, Inc. (http ://www.sequencedesign.com).
28. {28} "Modelsim," Model, Inc. (http://www.model.com).
29. {29} C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Mediabench: A tool for evaluating and synthesizing multimedia and communications systems," in Int. Symp. on Microarchitecture, 1997.