skip to main content
10.1109/ICCAD.2004.1382589acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
Article

Floorplan design for multi-million gate FPGAs

Published: 07 November 2004 Publication History

Abstract

Modern FPGAs have multi-millions of gates and future generations of FPGA will be even more complex. This means floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources on an FPGA, FPGA floorplanning is very different from the traditional floorplanning for ASICs. This work presents the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx's Spartan3 chips consisting of columns of CLBs, RAM blocks, and multiplier blocks). Our algorithm can generate floor-plans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes.

References

[1]
{1} Maogang Wang, Abhishek Ranjan, and Salil Raje. Multi-million gate FPGA physical design challenges. ICCAD, pages 891-898, 2003.
[2]
{2} D. Gregory, K. Bartlet, A. De Geus, and G. Hachtel. Socrates: a system for automatically synthesizing and optimizing combinational logic. DAC, pages 79-85, 1996.
[3]
{3} Robert Francis, Jonathan Rose, and Zvonko Vranesic. Chortle-crf: fast technology mapping for lookup table-based FPGAs. DAC, pages 227-233, 1991.
[4]
{4} C. Sechen and K. Lee. An improved simulated annealing algorithm for row-based placement. ICCAD, pages 478-481, 1987.
[5]
{5} J. Rose and S. Brown. Flexibility of interconnection structures in field-programmable gate arrays. IEEE Journal of Solid State Circuits, 26(3):277-282, March 1991.
[6]
{6} George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. Multilevel hypergraph partitioning: application in VLSI domain. DAC, pages 526-529, 1997.
[7]
{7} Ralph H. J. M. Otten. Automatic floorplan design. DAC, pages 261-267, 1982.
[8]
{8} H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based module palcement. ICCAD, pages 472-479, 1995.
[9]
{9} X. Hong et al. Comer Block List: an effective and efficient topological representation of nonslicing floorplan. ICCAD, pages 8-11, 2000.
[10]
{10} E. F. Y. Yong, C. C. N. Chu, and Z. C. Shen. Twin Binary Sequences: a nonredundant representation for general nonslicing floorplan. TCAD, 22(4):457-469, April 2003.
[11]
{11} J. M. Emmert and D. Bhatia. A methodology for fast FPGA floorplanning. International Symposium on Field Programmable Gate Arrays, 1999.
[12]
{12} http://www.xilinx.com.
[13]
{13} Larry J. Stockmeyer. Optimal orientations of cells in slicing floorplan designs. Information and Control, 57(2/3):91-101, 1983.
[14]
{14} D. F. Wong and C. L. Liu. A new algorithm for floorplan design. DAC, pages 101-107, 1986.

Cited By

View all
  • (2024)PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/367684917:3(1-31)Online publication date: 5-Aug-2024
  • (2022)Layout-oriented radiation effects mitigation in RISC-V soft processorProceedings of the 19th ACM International Conference on Computing Frontiers10.1145/3528416.3530984(215-220)Online publication date: 17-May-2022
  • (2012)PDPRProceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications10.1007/978-3-642-28365-9_31(350-356)Online publication date: 19-Mar-2012
  • Show More Cited By
  1. Floorplan design for multi-million gate FPGAs

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
    November 2004
    913 pages
    ISBN:0780387023

    Sponsors

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 07 November 2004

    Check for updates

    Qualifiers

    • Article

    Conference

    ICCAD04
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 457 of 1,762 submissions, 26%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)2
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 09 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/367684917:3(1-31)Online publication date: 5-Aug-2024
    • (2022)Layout-oriented radiation effects mitigation in RISC-V soft processorProceedings of the 19th ACM International Conference on Computing Frontiers10.1145/3528416.3530984(215-220)Online publication date: 17-May-2022
    • (2012)PDPRProceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications10.1007/978-3-642-28365-9_31(350-356)Online publication date: 19-Mar-2012
    • (2010)Hybrid evolutionary algorithm of planning VLSIProceedings of the 12th annual conference on Genetic and evolutionary computation10.1145/1830483.1830629(821-822)Online publication date: 7-Jul-2010
    • (2006)Timing-driven placement for heterogeneous field programmable gate arrayProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233578(383-388)Online publication date: 5-Nov-2006

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media