Article

Variability in sub-100nm SRAM designs

Authors:

P. WangAuthors Info & Claims

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Pages 347 - 352

https://doi.org/10.1109/ICCAD.2004.1382599

Published: 07 November 2004 Publication History

Abstract

Many components of variability become larger percentage design factors with decreasing feature size. Hence, the small transistors in SRAM cells are particularly sensitive to these variations. The SRAM cell transistors in sub-100-nm designs may contain fewer than 100 channel dopant atoms. To achieve a robust design with such variability, one must enhance the normal static-noise-margin and write-trip-point analysis, often with Monte Carlo simulations using statistical transistor models including the process and mismatch fluctuations. Similar challenges exist for the sense amplifiers normally used with SRAM arrays. Except with very low speed designs, yield to speed can be substantially reduced by variations between nominally matched sense amplifier transistors as well as by the variability resulting in a very worst memory cell low read current. This also increases the hazards of delay timing with dummy paths and dummy cells and increases the need for at-speed testing prior to repair.

References

[1]

{1} E. Seevinck Sr., F. List, J. Lohstroh; "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, pp. 748-754, Oct. 1987.

[2]

{2} K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE Journal of Solid-State Circuits, vol. 21, pp. 1057-1066, Dec. 1986.

[3]

{3} J. Croon, et. al., "Line Edge Roughness Characterization, Modeling and Impact on Device Behavior," IEDM, Dec. 2002.

[4]

{4} Semiconductor Industry Association (SIA), International Roadmap for Semiconductors 2001 edition, Austin Tx; International SEMITECH, 2001. Available: http://public.itrs.net.

[5]

{5} Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, pp. 201-204, Jun. 2000.

[6]

{6} A. Bhavnagarwala, X. Tang, J. Meindl; "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE Journal of Solid-State Circuits, vol. 36, pp. 658-665, April 2001.

[7]

{7} A. Hajimiri, R. Heald, "Design Issues in Cross-Coupled Inverter Sense Amplifier," ISCAS Dig. of Technical Papers, May 1998.

[8]

K. Bowman, B. Austin, J. Eble, X. Tang, J. Meindl; "A physical alpha-power law MOSFET model," IEEE Journal of Solid-State Circuits, vol. 34, pp. 1410-1414, October 1999.

[9]

K. Bowman, S. Duvall, J. Meindl; "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, February 2002.

[10]

K. Bowman, X. Tang, J. Eble, J. Meindl; "Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1186-1193, August 2000.

[11]

D. Burnett, K. Erington, C. Subramanian, K. Baker; "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits," Proc. Symp. VLSI Tech., pp. 15-16, June 1994.

[12]

J. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, H. Maes; "An easy-to-use mismatch model for the MOS transistor," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1056- 1064, August 2002.

[13]

P. Drennan, C. McAndrew; "A comprehensive MOSFET mismatch model," Proc. IEDM, Dec. 1999, pp. 167-170.

[14]

J. Lohstroh, E. Seevinck, J. de Groot; "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE Journal of Solid-State Circuits, vol. 18, pp. 803-807, December 1983.

[15]

J. Meindl, V. De, D. S. Wills, J. Eble, X. Tang, J. Davis, B. Austin, A. Bhavnagarwala; "The impact of stochastic dopant and interconnect distributions on gigascale integration," IEEE International Solid-State Circuits Conference, vol. XL, pp. 232-233, February 1997.

[16]

Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, "Review and future prospects of low-power RAM circuits," IBM Journal of Research and Development, vol. 47, no. 5/6, pp. 525- 552, September/November 2003.

Digital Library

[17]

C. Michael, M. Ismail; "Statistical modeling of device mismatch for analog MOS integrated circuits," IEEE Journal of Solid-State Circuits, vol. 27, pp. 154-166, February 1992.

[18]

P. A. Stolk, F. P. Widdershoven, D. B. M. Klaassen; "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Devices, vol. 45, pp. 1960-1971, Sept. 1998.

[19]

X. Tang, V. De, J. D. Meindl; "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. VLSI Syst., vol. 5, pp. 369-376, Dec. 1997.

Digital Library

[20]

X. Tang, V. K. De, J. D. Meindl; "MOSFET fluctuation limits on gigascale integration (GSI)," 1998 Eur. Solid-State Device Research Conf. (ESSDERC'98), Bordeaux, France, pp. 508- 511, Sept. 1998.

[21]

S.-C. Wong, K.-H. Pan, D.-J. Ma; "A CMOS mismatch model and scaling effects," IEEE Electron Device Lett., vol. 18, pp. 261-263, June 1997.

Cited By

Sun SLi XChang Y(2014)Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation spaceProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691430(324-331)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691430
Holcomb DFu K(2014)Bitline PUFProceedings of the 16th International Workshop on Cryptographic Hardware and Embedded Systems --- CHES 2014 - Volume 873110.1007/978-3-662-44709-3_28(510-526)Online publication date: 23-Sep-2014
https://dl.acm.org/doi/10.1007/978-3-662-44709-3_28
Chen CBowman KAugustine CZhang ZTschanz JChou PHuang RXie YKarnik T(2013)Minimum supply voltage for sequential logic circuits in a 22nm technologyProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648715(181-186)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.5555/2648668.2648715
Show More Cited By

Recommendations

Low-leakage robust SRAM cell design for sub-100nm technologies
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these ...
Circuit-level techniques to control gate leakage for sub-100nm CMOS
ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

Although still negligible for state-of-the-art CMOS, gate leakage will become significant in the future for sub-100nm technologies, due to the scaling of oxide thickness. We propose several circuit techniques to control gate leakage based on the fact ...
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
VLSID '05: Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design

An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and gate leakage power, is becoming more significant compared to dynamic power ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

November 2004

913 pages

ISBN:0780387023

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 07 November 2004

Check for updates

Qualifiers

Article

Conference

ICCAD04

Sponsor:

SIGDA

ICCAD04: The International Conference on Computer-Aided Design 2004

November 7 - 11, 2004

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

32
Total Citations
View Citations
530
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Sun SLi XChang Y(2014)Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation spaceProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691430(324-331)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691430
Holcomb DFu K(2014)Bitline PUFProceedings of the 16th International Workshop on Cryptographic Hardware and Embedded Systems --- CHES 2014 - Volume 873110.1007/978-3-662-44709-3_28(510-526)Online publication date: 23-Sep-2014
https://dl.acm.org/doi/10.1007/978-3-662-44709-3_28
Chen CBowman KAugustine CZhang ZTschanz JChou PHuang RXie YKarnik T(2013)Minimum supply voltage for sequential logic circuits in a 22nm technologyProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648715(181-186)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.5555/2648668.2648715
Sun SLi XLiu HLuo KGu BHenkel J(2013)Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation spaceProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561923(478-485)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561923
Shahid MRosenstiel WMacii E(2012)Cross entropy minimization for efficient estimation of SRAM failure rateProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492765(230-235)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492765
Sun ZBi XLi HShanbhag NPoncino MChou PAmerasekera A(2012)Process variation aware data management for STT-RAM cache designProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333706(179-184)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333706
Yoshimoto STerada MUmeki YOkumura SKawasumi ASuzuki TMoriwaki SMiyano SKawaguchi HYoshimoto MShanbhag NPoncino MChou PAmerasekera A(2012)A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) schemeProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333683(85-90)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333683
Gong FBasir-Kazeruni SDolecek LHe LHu JKoh C(2012)A fast estimation of SRAM failure rate using probability collectivesProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160926(41-48)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160926
Lorente VSahuquillo J(2012)Effects of process variation on the access time in SRAM cellsProceedings of the 18th international conference on Parallel processing workshops10.1007/978-3-642-36949-0_38(347-356)Online publication date: 27-Aug-2012
https://dl.acm.org/doi/10.1007/978-3-642-36949-0_38
Joshi RKanj RWang PLi HPhillips JHu AGraeb H(2011)Universal statistical cure for predicting memory lossProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132381(236-239)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132381
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten