A type architecture for hybrid micro-parallel computers

Programmable spatial fabrics, such as FPGAs, can provide some of the performance and efficiency benefits of custom hardware while retaining the low cost and flexibility of reprogrammable architectures. However, these fine-grained parallel architectures still have not been as widely adopted as many believe they could be for computationally intensive applications. The problem is two-fold: First, most applications contain substantial amounts of mostly sequential code that does not execute efficiently on a spatial fabric. Second, programming spatial architectures still requires some knowledge of the arcane arts of hardware engineering.Recently, hybrid processors that integrate a sequential processor with a spatial fabric have become prevalent. While hybrid computers ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics, remains challenging. Part of the difficulty lies in the lack of a commonly agreed upon computational model and family of programming languages.To address this challenge, we are developing a new type architecture--an abstract model analogous to the von Neumann machine for sequential computers--that can serve as common ground for algorithm designers, language designers, and hardware architects. We show how this model applies to several relevant architectures, and present examples of how it can effectively inform algorithm, language, and hardware design, thereby improving the programmability of hybrid processors.