Article

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime

Authors:

Roshan Weerasekera,

Dinesh Pamunuwa,

Hannu TenhunenAuthors Info & Claims

SLIP '06: Proceedings of the 2006 international workshop on System-level interconnect prediction

Pages 113 - 120

https://doi.org/10.1145/1117278.1117301

Published: 04 March 2006 Publication History

Abstract

In this paper we propose a smart repeater that consumes less energy and is suitable for driving global interconnections in nanometre technologies. When there is coupling between interconnects, the effective capacitance of a given wire is a function not only of the physical geometry, but also the relative switching pattern described by the bits on the wire in question (the victim) and the adjacent wires (aggressors). The drive strength of a traditional repeater is static, resulting in a spread of the propagation delay, with the repeater strength being essentially too much for every bit pattern other than the worst-case pattern. In the proposed SMART repeater, the drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. By disconnecting part of the repeater when it is not needed, the total load capacitance to the previous stage is reduced, resulting in reduced energy consumption for those instances. It is shown that the potential average saving in energy can be as much 15% with a 18% jitter reduction over a traditional repeater for typical global wire lengths in nanometre technologies.

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Cited By

Dobkin RMoyal MKolodny AGinosar R(2010)Asynchronous current mode serial communicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202085918:7(1107-1117)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2020859
Dobkin RMorgenshtein AKolodny AGinosar RMandoiu IKennings A(2008)Parallel vs. serial on-chip communicationProceedings of the 2008 international workshop on System level interconnect prediction10.1145/1353610.1353620(43-50)Online publication date: 5-Apr-2008
https://dl.acm.org/doi/10.1145/1353610.1353620
Weerasekera RPamunuwa DZheng LTenhunen H(2008)Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regimeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.91755516:5(589-593)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.917555
Show More Cited By

Index Terms

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
1. Hardware
  1. Very large scale integration design

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cover image ACM Conferences

SLIP '06: Proceedings of the 2006 international workshop on System-level interconnect prediction

March 2006

130 pages

ISBN:1595932550

DOI:10.1145/1117278

General Chair:
Mike Hutton
Altera, USA
,
Program Chair:
Joni Dambre
Ghent University, Belgium

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 March 2006

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SLIP06: International Workshop on System Level Interconnect Prediction

March 4 - 5, 2006

Munich, Germany

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Dobkin RMoyal MKolodny AGinosar R(2010)Asynchronous current mode serial communicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202085918:7(1107-1117)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2020859
Dobkin RMorgenshtein AKolodny AGinosar RMandoiu IKennings A(2008)Parallel vs. serial on-chip communicationProceedings of the 2008 international workshop on System level interconnect prediction10.1145/1353610.1353620(43-50)Online publication date: 5-Apr-2008
https://dl.acm.org/doi/10.1145/1353610.1353620
Weerasekera RPamunuwa DZheng LTenhunen H(2008)Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regimeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.91755516:5(589-593)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.917555
Dobkin RPerelman YLiran TGinosar RKolodny A(2007)High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data LinkProceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2007.20(3-14)Online publication date: 12-Mar-2007
https://dl.acm.org/doi/10.1109/ASYNC.2007.20

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