Constraint-driven bus matrix synthesis for MPSoC

ABSTRACT

Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses, which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9 X component savings when compared to a full bus matrix and up to 3.2 X savings when compared to a maximally connected reduced bus matrix.

REFERENCES

• 1: ARM AMBA Specification (rev2.0), www.arm.com, 2001
• 2: "IBM On-chip CoreConnect Bus Architecture", www.chips.ibm.com
• 3: "STBus Communication System: Concepts and Definitions", Reference Guide, STMicroelectronics, May 2003
• 4: "Sonics Integration Architecture, Sonics Inc", www.sonicsinc.com
• 5: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921 ]
• 6: Jörg Henkel , Wayne Wolf , Srimat Chakradhar, On-chip networks: A scalable, communication-centric embedded system design paradigm, Proceedings of the 17th International Conference on VLSI Design, p.845, January 05-09, 2004
• 7: M. Nakajima et al. "A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC", ISSCC 2002
• 8: Srinivasan Murali , Giovanni De Micheli, An Application-Specific Design Methodology for STbus Crossbar Generation, Proceedings of the conference on Design, Automation and Test in Europe, p.1176-1181, March 07-11, 2005 [doi>10.1109/DATE.2005.50]
• 9: V. Lahtinen, et al, "Comparison of synthesized bus and crossbar interconnection architectures", ISCAS 2003
• 10: K. K Ryu, E. Shin, V. J. Mooney, "A Comparison of Five Different Multiprocessor SoC Bus Architectures", DSS 2001
• 11: Mirko Loghi , Federico Angiolini , Davide Bertozzi , Luca Benini , Roberto Zafalon, Analyzing On-Chip Communication in a MPSoC Environment, Proceedings of the conference on Design, automation and test in Europe, p.20752, February 16-20, 2004
• 12: Michael Gasteier , Manfred Glesner, Bus-based communication synthesis on system level, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.1-11, Jan. 1999 [doi>10.1145/298865.298866]
• 13: Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Automated throughput-driven synthesis of bus-based communication architectures, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120920]
• 14: Sudeep Pasricha , Nikil Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, Floorplan-aware automated synthesis of bus-based communication architectures, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065727]
• 15: Krishnan Srinivasan , Karam S. Chatha , Goran Konjevod, Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.422-429, October 11-13, 2004
• 16: Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005 [doi>10.1109/TPDS.2005.22]
• 17: Osamu Ogawa , Sylvain Bayon de Noyer , Pascal Chauvet , Katsuya Shinohara , Yoshiharu Watanabe , Hiroshi Niizuma , Takayuki Sasaki , Yuji Takai, A Practical Approach for Bus Architecture Optimization at Transaction Level, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20176, March 03-07, 2003
• 18: SystemC initiative. www.systemc.org
• 19: Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Fast Exploration of Bus-Based On-Chip Communication Architectures, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04), p.242-247, September 08-10, 2004 [doi>10.1109/CODES+ISSS.2004.30]
• 20: S. Pasricha, N. Dutt, M. Ben-Romdhane, "Bus Matrix Communication Architecture Synthesis", CECS Technical Report 05--17, October 2005
• 21: ARM AMBA AXI Specification www.arm.com/armtech/AXI
• 22: Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Extending the transaction level modeling approach for fast communication architecture exploration, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996603]
• 23: Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Efficient exploration of the SoC communication architecture design space, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 24: S. Pasricha, "Transaction Level Modeling of SoC with SystemC 2.0" Synopsys User Group Conference (SNUG 2002), Bangalore, May 2002

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance