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Process-induced skew reduction in nominal zero-skew clock trees

Published: 24 January 2006 Publication History

Abstract

This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framework is used in a new algorithm that constructs deterministic nominal zero-skew clock trees that have reduced sensitivity to process variation. The new algorithm uses a sampling approach to perform route embedding during a bottom-up merging phase, but does not select the best embedding until the top-down phase. This results in clock trees that exhibit a mean skew reduction of 32.4% on average and a standard deviation reduction of 40.7% as verified by Monte Carlo. The average increase in total clock tree capacitance is less than 0.02%.

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Cited By

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  • (2014)Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesisIntegration10.1016/j.vlsi.2013.12.00547:4(476-486)Online publication date: Sep-2014
  • (2014)Variability-Aware Clock DesignCircuit Design for Reliability10.1007/978-1-4614-4078-9_12(255-272)Online publication date: 16-Oct-2014
  • (2013)Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizesProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451956(154-161)Online publication date: 24-Mar-2013
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Published In

cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2014)Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesisIntegration10.1016/j.vlsi.2013.12.00547:4(476-486)Online publication date: Sep-2014
  • (2014)Variability-Aware Clock DesignCircuit Design for Reliability10.1007/978-1-4614-4078-9_12(255-272)Online publication date: 16-Oct-2014
  • (2013)Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizesProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451956(154-161)Online publication date: 24-Mar-2013
  • (2012)High-performance clock mesh optimizationACM Transactions on Design Automation of Electronic Systems10.1145/2209291.220930617:3(1-17)Online publication date: 5-Jul-2012
  • (2010)Novel binary linear programming for high performance clock mesh synthesisProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133522(438-443)Online publication date: 7-Nov-2010
  • (2008)Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyondProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356860(220-225)Online publication date: 21-Jan-2008
  • (2008)Statistical Timing AnalysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2007.90704727:4(589-607)Online publication date: 1-Apr-2008
  • (2008)Design for manufacturing meets advanced process control: A surveyJournal of Process Control10.1016/j.jprocont.2008.04.00718:10(975-984)Online publication date: Dec-2008

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