High-throughput decoder for low-density parity-check code

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High-throughput decoder for low-density parity-check code

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with EDA Technofair Design Automation Conference Asia and South Pacific archive
Proceedings of the 2006 conference on Asia South Pacific design automation table of contents

Yokohama, Japan

SESSION: University design contest table of contents

Pages: 112 - 113

Year of Publication: 2006

ISBN:0-7803-9451-8

Authors

Tatsuyuki Ishikawa	Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan
Kazunori Shimizu	Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan
Takeshi Ikenaga	Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan
Satoshi Goto	Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM : Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

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ABSTRACT

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm².

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mohammad M. Mansour , Naresh R. Shanbhag, Low-power VLSI decoder architectures for LDPC codes, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566483]
	2	Marjan Karkooti , Joseph R. Cavallaro, Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding, Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2, p.579, April 05-07, 2004