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Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

Published: 24 January 2006 Publication History

Abstract

Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper will provide a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. First, effects at the micro scale---in interconnects and devices and their implications for performance, reliability and design are discussed. Next, macro scale---circuit and system level issues including substrate temperature gradients as well as strong ET couplings between supply voltage, frequency, power dissipation and junction temperature in leakage dominant technologies are outlined. A recently developed system level ET analysis methodology and tool that comprehends ET couplings in a self-consistent manner and can generate accurate thermal profile of the substrate is summarized. The application of the ET-tool is demonstrated in a number of areas from power-performance-cooling cost tradeoff analysis to circuit optimization, full-chip leakage estimation, and temperature/reliability aware design space generation. Implications of chip cooling for nanometer scale bulk and SOI based CMOS technologies are also discussed. The ET analysis tool is also shown to be useful for hot-spot management. The paper ends with a brief discussion of electrothermal issues in emerging 3-D ICs and highlights the advantages of employing hybrid Carbon Nanotube-Cu interconnects in both 2-D and 3-D designs.

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  1. Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

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          cover image ACM Conferences
          ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
          January 2006
          998 pages
          ISBN:0780394518

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          • IEEE Circuits and Systems Society
          • SIGDA: ACM Special Interest Group on Design Automation
          • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
          • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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          Published: 24 January 2006

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          • (2019)Analytical Thermal Model for Self-Heating Effects in Advanced FinFET Devices2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)10.1109/ICTA48799.2019.9012894(107-108)Online publication date: Nov-2019
          • (2013)A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as VLSI InterconnectionIEEE Transactions on Nanotechnology10.1109/TNANO.2011.215901412:1(3-12)Online publication date: 1-Jan-2013
          • (2013)Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and ReliabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.224819432:7(1045-1058)Online publication date: 1-Jul-2013
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          • (2007)A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal ModelIEEE Transactions on Electron Devices10.1109/TED.2007.90903954:12(3342-3350)Online publication date: 2007
          • (2007)Analyzing Conductance of Mixed Carbon-Nanotube Bundles for Interconnect ApplicationsIEEE Electron Device Letters10.1109/LED.2007.90158428:8(756-759)Online publication date: Aug-2007
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