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Wire sizing with scattering effect for nanoscale interconnection

Published: 24 January 2006 Publication History

Abstract

For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physics-based models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closed-form scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70% underestimation of the delay, or 20x oversizing. We also obtain the new closed-form wiresizing functions with consideration of scattering effects.

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Cited By

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  • (2022)Heterogeneous Integration at ScaleAdvances in Semiconductor Technologies10.1002/9781119869610.ch1(1-24)Online publication date: 30-Sep-2022
  • (2011)E-beam lithography stencil planning and optimization with overlapped charactersProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960433(151-158)Online publication date: 27-Mar-2011
  • (2008)Interconnect modeling for improved system-level design optimizationProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356868(258-264)Online publication date: 21-Jan-2008

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cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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Cited By

View all
  • (2022)Heterogeneous Integration at ScaleAdvances in Semiconductor Technologies10.1002/9781119869610.ch1(1-24)Online publication date: 30-Sep-2022
  • (2011)E-beam lithography stencil planning and optimization with overlapped charactersProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960433(151-158)Online publication date: 27-Mar-2011
  • (2008)Interconnect modeling for improved system-level design optimizationProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356868(258-264)Online publication date: 21-Jan-2008

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