Wire sizing with scattering effect for nanoscale interconnection

ABSTRACT

For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physics-based models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closed-form scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70% underestimation of the delay, or 20x oversizing. We also obtain the new closed-form wiresizing functions with consideration of scattering effects.

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Index Terms

• Hardware

  • Electronic design automation

    • Physical design (EDA)

  • Hardware validation

  • Integrated circuits

    • Interconnect

  • Very large scale integration design