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FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

Published: 24 January 2006 Publication History

Abstract

This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.

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Cited By

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  • (2008)GECOMProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356943(577-582)Online publication date: 21-Jan-2008
  • (2008)GECOM: Test data compression combined with all unknown response masking2008 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2008.4484018(577-582)Online publication date: Jan-2008
  • (2007)A selective pattern-compression scheme for power and test-data reductionProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326180(520-525)Online publication date: 5-Nov-2007
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  1. FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

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          cover image ACM Conferences
          ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
          January 2006
          998 pages
          ISBN:0780394518

          Sponsors

          • IEEE Circuits and Systems Society
          • SIGDA: ACM Special Interest Group on Design Automation
          • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
          • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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          IEEE Press

          Publication History

          Published: 24 January 2006

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          Overall Acceptance Rate 466 of 1,454 submissions, 32%

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          Cited By

          View all
          • (2008)GECOMProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356943(577-582)Online publication date: 21-Jan-2008
          • (2008)GECOM: Test data compression combined with all unknown response masking2008 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2008.4484018(577-582)Online publication date: Jan-2008
          • (2007)A selective pattern-compression scheme for power and test-data reductionProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326180(520-525)Online publication date: 5-Nov-2007
          • (2007)CacheCompressProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326178(509-512)Online publication date: 5-Nov-2007
          • (2007)Scan Test Cost and Power Reduction Through Systematic Scan ReconfigurationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88458226:5(907-918)Online publication date: 1-May-2007
          • (2007)Cachecompress: a novel approach for test data compression with cache for IP embedded cores2007 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2007.4397315(509-512)Online publication date: Nov-2007
          • (2007)A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos16th Asian Test Symposium (ATS 2007)10.1109/ATS.2007.41(91-94)Online publication date: Oct-2007
          • (2006)Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain ClustersProceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems10.1109/DFT.2006.41(136-144)Online publication date: 4-Oct-2006

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