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Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs

Published: 24 January 2006 Publication History

Abstract

In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of Block Preference Directed Graph (BPDG) and the classic Sequence Pair (SP) floorplan representation. Given a set of analog and digital blocks, the BPDG is constructed based on their inherent noise characteristics to capture their preferred relative orders for substrate noise minimization. For each sequence pair generated during floorplanning evaluation, we can measure its violation against BPDG very efficiently. We observe that by simply counting the number of violations obtained in this manner, it correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model has high fidelity to guide the substrate noise-aware floorplanning and layout optimization, which become a growing concern for mixed-signal/RF system on chips (SOC). Our experimental results show that the proposed approach is over 60x faster than conventional floorplanning with even very compact substrate noise models. We also obtain less area and total substrate noise than the conventional approach.

References

[1]
A. Nardi, H. Zeng, J. L. Garrett, L. Daniel, and A. L. S-Vincentelli, "A Methodology for the computation of an upper bound on noise current spectrum of CMOS swichting activity," in Proc. Int. Conf. on Computer Aided Design, 2003, pp. 778--785.
[2]
A. Koukab, K. Banerjee, and M. Declercq, "Modeling Techniques and Verification Methdologies for Substrate Coupling Effects in Mixed-signal System-on-Chip designs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, Jun 2004.
[3]
M. V. Heijingen, M. Badarouglu, S. Donnay, G. G. E. Gielen, and H. J. D. Man, "Substrate Noise Generation in Complex Digital systems: efficient modeling and simulation methodology and experiemental verification," IEEE J. Solid-State Circuits, vol. 37, Aug 2002.
[4]
H. Lan, Z. Yu, and R. W. Dutton, "A CAD-oriented Modeling Approach of frequency-dependent behavior of Substrate Noise Coupling for Mixed-Signal IC Design," in Proc. Int. Symp. on Quality Electronic Design, Mar 2003, pp. 195--200.
[5]
B. Owens, S. Adluri, P. Birrer, R. Shreeve, S. K. Arunachalam, and K. Mayaram, "Simulation and Measurement of Supply and Substrate Noise in Mixed-Signal ICs," IEEE J. Solid-State Circuits, vol. 40, no. 2, Feb 2005.
[6]
T. Blalack, Y. Leclercq, and C. P. Yue, "On-chip RF isolation techniques," in Proc. IEEE BCTM., 2002, pp. 205--211.
[7]
C. Lin and D. Leenaerts, "A New Efficient Method Substrate-Aware Device-Level Placement," in Proc. Asia and South Pacific Design Automation Conf., 2000, pp. 533--536.
[8]
G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske, and J. S. Zhang, "Substrate Noise Modeling in Early Floorplanning of Mixed-Signal SOCs," in Proc. Asia and South Pacific Design Automation Conf., Jan 2005, pp. 819--823.
[9]
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair," vol. 15, Dec 1996.
[10]
X. Tang and D. Wong, "Floorplanning with Alignment and Performance Constraints," in Proc. Design Automation Conf., Jun 2002.
[11]
W. K. Chu, N. Verghese, K. S. H. Cho, H. Tsujikawa, S. Hirano, S. Doushoh, M. Nagata, A. Iwata, and T. Ohmoto, "A Substrate Noise Analysis Methodology for Large-Scale Mixed-Signal ICs," in Proc. IEEE Custom Integrated Circuits Conf., 2003.
[12]
N. K. Verghese and J. J. Allstot, "Computer-aided design considerations in Mixed-signal coupling in RF integration circuits," IEEE J. Solid-State Circuits, vol. 33, Mar 1998.
[13]
J. P. Costa, M. Chou, and L. M. Silveria, "Efficient techniques for accurate modeling and simulation of substrate coupling in Mixed-signal ICs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 5, pp. 597--607, May 1999.
[14]
D. Ozis, T. Fiez, and K. Mayaram, "An Efficient Modeling Approach for Substrate Noise Coupling Analysis," in Proc. IEEE Int. Symp. on Circuits and Systems, 2002.
[15]
D. Ozis, T. Fiez, and K. Mayaram, "Comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped cmos processes," in Proc. IEEE Custom Integrated Circuits Conf., 2002.
[16]
http://www.cse.ucsc.edu/research/surf/GSRC/MCNC.
[17]
S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical Design," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 120--1135, Dec 2003.
[18]
http://vlsicad.eecs.umich.edu/BK/parquet.
[19]
U. Brenner and A. Rohe, "An effective congestion driven placemnet framework," in Proc. Int. Symp. on Physical Design, 2002, pp. 6--11.

Cited By

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  • (2017)A substrate noise reduction methodology based on power domain separation of GALS subcomponents2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2017.8106981(1-6)Online publication date: Sep-2017
  • (2016)Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A SurveyElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-22(479-499)Online publication date: 14-Apr-2016
  • (2010)Fidelity metrics for estimation modelsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133431(1-8)Online publication date: 7-Nov-2010
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cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

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  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2017)A substrate noise reduction methodology based on power domain separation of GALS subcomponents2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2017.8106981(1-6)Online publication date: Sep-2017
  • (2016)Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A SurveyElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-22(479-499)Online publication date: 14-Apr-2016
  • (2010)Fidelity metrics for estimation modelsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133431(1-8)Online publication date: 7-Nov-2010
  • (2010)Fidelity metrics for estimation models2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5653959(1-8)Online publication date: Nov-2010
  • (2009)On minimizing various sources of noise and meeting symmetry constraint in mixed-signal SoC floorplan design2009 1st Asia Symposium on Quality Electronic Design10.1109/ASQED.2009.5206291(96-102)Online publication date: Jul-2009
  • (2009)FloorplanningElectronic Design Automation10.1016/B978-0-12-374364-0.50017-5(575-634)Online publication date: 2009
  • (2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
  • (2007)Physical Design for System-On-A-ChipEssential Issues in SOC Design10.1007/1-4020-5352-5_9(311-403)Online publication date: 2007
  • (2006)Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and ValidationProceedings of the IEEE10.1109/JPROC.2006.88602994:12(2109-2138)Online publication date: Dec-2006

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