Controlling inductive cross-talk and power in off-chip buses using CODECs

ABSTRACT

The parasitic inductances within IC packaging cause supply bounce as well as glitches on the signal pins, significantly limiting the frequency of high-speed inter-chip communication. Also, off-chip communication contributes a large fraction of the total system power. Until recently, the parasitic inductance problem was addressed by aggressive package design, which is expensive. In this work we present a technique to encode the off-chip data transmission to i) limit bounce on the supplies ii) reduce glitching caused by inductive signal coupling from neighboring signals iii) limit the edge degradation of signals due to mutually inducted voltages from neighboring switching signals and iv) control the total power consumption of the I/O logic. All these factors are modeled in a unified mathematical framework. Our experimental results show that the proposed encoding based techniques result in reduced supply bounce and signal glitching due to inductive cross-talk, closely matching the theoretical predictions. Also, we show that the bus size overhead is reasonable even after stringent power reduction constraints are imposed. We demonstrate that the overall bandwidth of a bus actually increases by 100% over an unencoded bus, using our technique with inductive constraints only (even after accounting for the encoding overhead). When the power constraints were added (to limit the power to 20% of worst case switching power) in addition to the inductive constraints, the bandwidth was again 100% improved over the unencoded bus. The asymptotic bus size overhead depends on how stringent the user-specified power and inductive cross-talk parameters are. We have validated our approach by simulating it in an ASIC setting as well as prototyping and testing it in an FPGA environment.

References

1. "The International Technology Roadmap for Semiconductors." http://public.itrs.net, 2003.]]
2. R. Tummalo, Fundamentals of Microsystem Packaging. McGraw-Hill, 2001.]]
3. M. Miura, N. Hirano, Y. Hiruta, and T. Sudo, "Electrical characterization and modeling of simultaneous switching noise for leadframe packages," in Proceedings of 45th Electronic Components and Technology Conference, pp. 857--864, May 1995.]]
4. B. Young, "Return path inductance in measurements of package inductance matrixes," in IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 20, Feb 1997.]]
5. N. Hirano, M. Miura, Y. Hiruta, and T. Sudo, "Characterization and reduction of simultaneous switching noise for a multilayer package,"]]
6. R. E. Bryant, "Graph based algorithms for Boolean function representation," IEEE Transactions on Computers, vol. C-35, pp. 677--690, August 1986.]]
7. M. Lopez, J. Prince, and A. Cangellaris, "Influence of a floating plane on effective ground plane inductance in multilayer and coplanar packages," in IEEE Transactions on Advanced Packaging, vol. 22, pp. 182--188, May 1999.]]
8. C. Duan, A. Tirumala, and S. Khatri, "Analysis and avoidance of cross-talk in on-chip buses," IEEE Symposium on High-Performance Interconnects (HOT Interconnects), pp. 133--138, Aug 2001.]]
9. C. Duan and S. Khatri, "Exploiting crosstalk to speed up on-chip buses," Design Automation and Test in Europe Conference, Feb 2004.]]
10. B. Victor and K. Keutzer, "Bus encoding to prevent crosstalk delay," in Proceedings, IEEE/ACM International Conference on Computer Aided Design, (San Jose, CA), pp. 57--63, Nov 2001.]]
11. M. Stan and W. Burleson, "Bus-invert coding for low-power I/O" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, pp. 49--58, Mar 1995.]]
12. P. Sotiriadis and A. Chandrakasan, "Reducing bus delay in submicron technology using coding," in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 109--114, Jan-Feb 2001.]]
13. T. Lv, J. Henkel, H. Lekatsas, and W. Wolf, "A dictionary-based en/decoding scheme for low-power data buses," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 943--951, Oct 2003.]]
14. B. LaMeres and S. Khatri, "Encoding-based minimization of inductive cross-talk for off-chip data transmission," in Proceedings, Design Automation and Test in Europe (DATE) Conference, (Munich, Germany), Mar 2005.]]
15. M. Powell and T. Vijaykumar, "Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage," in Proceedings of 30th International Symposium on Computer Architecture, pp. 72--83, June 2003.]]
16. C. Chen and B. Curran, "Switching codes for delta-i noise reduction," in IEEE Transactions of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 45, pp. 1017 -- 1021, Sept 1996.]]
17. E. Mejia-Motta, F. Sandoval-Ibarra, and J. Santana, "Design of cmos buffers using the settling time of the ground bounce voltage as a key parameter," in Proceedings of 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 718--721, Aug 2000.]]

Index Terms

• Hardware

  • Hardware validation

  • Integrated circuits

    • Logic circuits