Cache size selection for performance, energy and reliability of time-constrained systems

ABSTRACT

Improving performance, reducing energy consumption and enhancing reliability are three important objectives for embedded computing systems design. In this paper, we study the joint impact of cache size selection on these three objectives. For this purpose, we conduct extensive fault injection experiments on five benchmark examples using a cycle-accurate processor simulator. Performance and reliability are analyzed using the performability metric. Overall, our experiments demonstrate the importance of a careful cache size selection when designing energy-efficient and reliable systems. Furthermore, the experimental results show the existence of optimal or Pareto-optimal cache size selection to optimize the three design objectives.

References

1. J. L. Hennessy, D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd Edition, Morgan Kaufmann Publishing Co. 1996.
2. C. Zhang, F. Vahid and R. Lysecky, "A self-Tuning Cache Architecture for Embedded Systems", in Proc. of DATE, 2004.
3. C. Zhang, F. Vahid, W. Najjar, "A Highly Configurable Cache Architecture for Embedded Systems", in Proc. of International Symposium on Computer Architecture, 2003.
4. S. Dropsho et al., "Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power", in Proc. of the International Conference on Parallel Architectures and Compilation Techniques, 2002.
5. D. H. Albonesi, "Selective cache ways: On-demand cache resource allocation", in Proc. of International Symposium on Microarchitecutre, 1999.
6. M. Powell A. Agaewal, T. Vijaykumar, B. Falsafi and K. Roy, "Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct Mapping", in Proc. of International Symposium on Microarchitecture, 2001.
7. A. C. Nacul and T. Givargis, "Dynamic Voltage and Cache Reconfiguration for Low Power", in Proc. of DATE 04, March, 2004.
8. S. Yang, M. D. Powell, B. Falsafi, T. N. Vijaykumar, "Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay", in Proc. of International Symposium on High-Performance Computer Architecture, 2002.
9. G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, "Balancing Performacne and Reliability in the Memory Hierarchy", in Proc. of International Symposium on Performance Analysis of Systems and Software, 2005.
10. L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, "Soft Error and Energy Consumption interations: A Data Cache Perspective". in Proc. of ISLPED 04, Aug, 2004.
11. S. Kim and A. K. Somani, "Area Efficient Architectures for Information Integrity in Cache Memories", in Proc. of International Symposium on Computer Architecture, 1999.
12. W. Zhang, S. Gurumurthi, M. Kandemir, A. Sivasubramaniam, "ICR: in-cache replication for enhancing data cache reliability", in Proc. of International Conference on Dependable Systems and Networks, 2003.
13. D. Zhu, R. Melhem. and D. Mosse, "The Effecs of Energy Management on Reliability in Real-Time Embedded Systems", in Proc. of ICCAD 04, Nov. 2004.
14. A. Ejlali, M. T. Schmitz, B. M. Al-Hashimi, S. G. Miremadi, "Energy Efficient SEU-Tolerance in DVS-Enabled Real-Time Systems through Information Redundancy", in Proc. of ISLPED 05, Aug. 2005.
15. R. Melhem, D. Mosse, E. Elnozahy, "The interplay of Power Management and Fault Recovery in Real-Time Systems", IEEE Transaction on Computers, Vol. 53, No. 2, February, 2004.
16. H. Hanson, M. S. Hrishikesh, V. Agarwal, S. W. Keckler, D. Burger, "Static Energy Reduction Techniques for Microprocessor Caches", IEEE Transaction on VLSI systems, Vol. 11, No. 3, June, 2003.
17. S. Mitra, N. Seifert, M. Zhang, Q. Shi, K. S. Kim, "Robust System Design with Built-In Soft-Error Resilience", IEEE Computer Magazine, Vol, 38, No. 2, Feburary, 2005.
18. P. E. Dodd and F. W. Sexton, "Critical Charge Concepts for the CMOS SRAMS", IEEE Transactions on Nuclear Science, Vol. 42, No. 6, Dec. 1995.
19. F. Faure, R. Velazco, M. Violante, M. Rebaudengo and M. Sonza Reorda, "Impact of Data Cache Memory on the Single Event Upset-Induced Error Rate of Microprocessors", IEEE Transactions on Nuclear Science, Vol. 50, No. 6, Dec. 2003.
20. A. Maheshwari, W. Burleson, R. Tessier, "Trading off Transient Fault Tolerance and Power Consumption in Deep Submicron (DSM) VLSI Circuits", IEEE Transaction on VLSI systems, Vol. 12, No. 3, March 2004.
21. M. Rebaudengo, M. S. Reorda and M. Violante, "An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor", in Proc. of DATE 03, March, 2003.
22. L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and A. Sivsubramaniam, "Leakage Energy Management in Cache Hierarchies", in Proc. of International Conference on Parallel Architectures and Compilation Techniques, 2002.
23. G. Reinmann and N. P. Jouppi, "CACTI2.0: An Integrated Cache Timing and Power Model", COMPAQ, Western Research Lab, Research Report, 2000.
24. http://www-micrel.deis.unibo.it/sitonew/research/mparm.html

Index Terms

• Hardware

  • Hardware test

  • Hardware validation

  • Integrated circuits

    • Semiconductor memory

      • Dynamic memory

  • Robustness