| An integrated performance and power model for superscalar processor designs |
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with EDA Technofair Design Automation Conference Asia and South Pacific
archive
Proceedings of the 2005 conference on Asia South Pacific design automation
table of contents
Shanghai, China
SESSION: Poster session I
table of contents
Pages: 948 - 951
Year of Publication: 2005
ISBN:0-7803-8737-6
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Downloads (6 Weeks): 1, Downloads (12 Months): 25, Citation Count: 0
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ABSTRACT
On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance constraints. This paper describes an integrated performance and power analytical model. The model's performance and power results are in good agreement with detailed simulations, previous models and physically measured results. For designers, the model enables quick and flexible explorations into a subset of even entire huge parameter space of more than 15 workload and architectural parameters plus leakage power, feature sizes, clock and voltage.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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T. Austin, D. Burger, G. Sohi, M. Franklin, S. Breach, and K. Skadron. The simplescalar architectural research tool set. In Available online, http://www.cs.wisc.edu/mscalar/simplescalar.html, 1998.
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David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000
[doi> 10.1109/40.888701
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J. F. Cantin and M. D. Hill. Cache performance for spec cpu2000 benchmarks, version 3.0. In Available online, http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data/, 2004.
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K. Khouri and N. Jha. Leakage power analysis and reduction during behavioral synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(6):876--885, December 2002.
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Y. Pyun, C. Park, and S. Choi. The effect of instruction window on the performance of superscalar processors. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E81A(6):1036--1044, June 1998.
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Viji Srinivasan , David Brooks , Michael Gschwind , Pradip Bose , Victor Zyuban , Philip N. Strenski , Philip G. Emma, Optimizing pipelines for power and performance, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
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J. Sulstyo and D. S. Ha. A new characterization method for delay and power dissipation of standard library cells. VLSI Design, 15(3):667--678, 2002.
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Sun. Ultrasparc III Cu processor. In Available online, http://www.sun.com/processors/UltraSPARCIII/DS00101USIIICu0902.pdf. Sun Microsystems, 2001.
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D. Sylvester, W. Jiang, and K. Keutzer. Bacpac - Berkeley Advanced Chip Performance Calculator. In Available online, http://www.eecs.umich.edu/ dennis/bacpac/, 1998.
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N. Vijaykrishnan , M. Kandemir , M. J. Irwin , H. S. Kim , W. Ye, Energy-driven integrated hardware-software optimizations using SimplePower, Proceedings of the 27th annual international symposium on Computer architecture, p.95-106, June 2000, Vancouver, British Columbia, Canada
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