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An integrated performance and power model for superscalar processor designs
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Source with EDA Technofair Design Automation Conference Asia and South Pacific archive
Proceedings of the 2005 conference on Asia South Pacific design automation table of contents
Shanghai, China
SESSION: Poster session I table of contents
Pages: 948 - 951  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Yongxin Zhu  National University of Singapore, Singapore
Weng-Fai Wong  National University of Singapore, Singapore
Ştefan Andrei  National University of Singapore, Singapore
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance constraints. This paper describes an integrated performance and power analytical model. The model's performance and power results are in good agreement with detailed simulations, previous models and physically measured results. For designers, the model enables quick and flexible explorations into a subset of even entire huge parameter space of more than 15 workload and architectural parameters plus leakage power, feature sizes, clock and voltage.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Yongxin Zhu: colleagues
Weng-Fai Wong: colleagues
Ştefan Andrei: colleagues