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Post-layout logic duplication for synthesis of domino circuits with complex gates

Authors:

Aiqun Cao,

Ruibing Lu,

Cheng-Kok KohAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 260 - 265

https://doi.org/10.1145/1120725.1120845

Published: 18 January 2005 Publication History

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Abstract

Logic duplication to resolve the logic reconvergent paths problem encountered in Domino logic synthesis is expensive in terms of area and power. In this paper, we propose a combined logic duplication minimization and technology mapping scheme for Domino circuits with complex gates. The logic duplication is performed as a post-layout step as the duplication cost is minimized based on accurate timing information. Experimental results show significant improvements in area, power, and delay.

References

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Morgenshtein AFriedman EGinosar RKolodny A(2010)Unified logical effortIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201423918:5(689-696)Online publication date: 1-May-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2014239
Morgenshtein AFriedman EGinosar RKolodny AMandoiu IKennings A(2008)Timing optimization in logic with interconnectProceedings of the 2008 international workshop on System level interconnect prediction10.1145/1353610.1353615(19-26)Online publication date: 5-Apr-2008
https://dl.acm.org/doi/10.1145/1353610.1353615

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Postlayout optimization for synthesis of Domino circuits

Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this article, we propose a synthesis scheme to reduce the duplication cost by allowing ...

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ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 18 January 2005

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SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Morgenshtein AFriedman EGinosar RKolodny A(2010)Unified logical effortIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201423918:5(689-696)Online publication date: 1-May-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2014239
Morgenshtein AFriedman EGinosar RKolodny AMandoiu IKennings A(2008)Timing optimization in logic with interconnectProceedings of the 2008 international workshop on System level interconnect prediction10.1145/1353610.1353615(19-26)Online publication date: 5-Apr-2008
https://dl.acm.org/doi/10.1145/1353610.1353615

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Post-layout logic optimization of domino circuits

The synthesis method of logic circuits based on the iMemComp gates

Postlayout optimization for synthesis of Domino circuits

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