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Floorplan management: incremental placement for gate sizing and buffer insertion

Published: 18 January 2005 Publication History

Abstract

Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental changes to the layout and netlist due to physical synthesis techniques without perturbing the original metrics. We present an incremental placement approach using floorplan sizing to manage the resources and demands of the whole chip region in order to accommodate the changes due to gate sizing and buffer insertion. The experimental results show that this approach can accommodate a wide range of incremental changes without a loss in wirelength and routability. Most important, it also maintains the stability of a placement such that the convergence of physical synthesis iterations can be greatly enhanced.

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Cited By

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  • (2017)An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designsProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199766(496-503)Online publication date: 13-Nov-2017
  • (2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
  • (2009)Incremental buffer insertion and module resizing algorithm using geometric programmingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531636(413-416)Online publication date: 10-May-2009
  • Show More Cited By

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 January 2005

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Cited By

View all
  • (2017)An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designsProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199766(496-503)Online publication date: 13-Nov-2017
  • (2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
  • (2009)Incremental buffer insertion and module resizing algorithm using geometric programmingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531636(413-416)Online publication date: 10-May-2009
  • (2008)Optimizing non-monotonic interconnect using functional simulation and logic restructuringProceedings of the 2008 international symposium on Physical design10.1145/1353629.1353653(95-102)Online publication date: 13-Apr-2008
  • (2008)SafeResynthIntegration, the VLSI Journal10.1016/j.vlsi.2008.01.00441:4(544-556)Online publication date: 1-Jul-2008
  • (2007)Placement for Power OptimizationClosing the Power Gap Between ASIC & Custom10.1007/978-0-387-68953-1_9(219-249)Online publication date: 2007
  • (2007)Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental CapabilityModern Circuit Placement10.1007/978-0-387-68739-1_5(97-133)Online publication date: 2007
  • (2005)Recursive bisection placementProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055186(230-232)Online publication date: 3-Apr-2005

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