A design of high speed double precision floating point adder using macro modules

ABSTRACT

Based on SMIC 0.18 μm 1.8v six-layer-metal CMOS process, we implement a 64-bit high speed pipelined floating point adder which satisfied IEEE 754 standard. After the critical path analysis of the pipelined structure, we custom design three macro modules in order to reduce critical path delay. After placement in datapath style and routing, we implement the layout of floating point adder. The chip area is 1.44 mm² and clock frequency is 518MHz.

REFERENCES

• 1: Stuart Franklin Oberman, Design issues in high performance floating point arithmetic units, Stanford University, Stanford, CA, 1997
• 2: Javier D. Bruguera , Tomás Lang, Leading-One Prediction with Concurrent Position Correction, IEEE Transactions on Computers, v.48 n.10, p.1083-1097, October 1999 [doi>10.1109/12.805157 ]
• 3: R. Zimmerman, "Binary Adder Architectures for Cell-Based VLSI and their Synthesis", PhD thesis, Swiss Federal Institute of Technology, Zurich, 1997.
• 4: Nhon T. Quach , Michael J. Flynn, An improved algorithm for high-speed floating-point addition, Stanford University, Stanford, CA, 1990
• 5: Peter-Michael Seidel , Guy Even, Delay-Optimized Implementation of IEEE Floating-Point Addition, IEEE Transactions on Computers, v.53 n.2, p.97-113, February 2004 [doi>10.1109/TC.2004.1261822]
• 6: Peter-Michael Seidel , Guy Even, On the Design of Fast IEEE Floating-Point Adders, Proceedings of the 15th IEEE Symposium on Computer Arithmetic, p.184, June 11-13, 2001