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Design and implementation of an SDH high-speed switch

Published: 18 January 2005 Publication History

Abstract

In this shot paper, we propose a design of SDH High-Speed Switch, which can switch 16x16 STM-16 streams with speed at 2.488 Gbit/s. In this design a novel fabric structure was used to perform non-blocking connection of STM-1 data in any timeslot of 16-bit parallel STM-16 data rate at 155.5MB/s. The prototype of the design is implemented in Altera's StratixTM GX FPGA devices. The test results show that the prototype meets all requirements.

References

[1]
Altera Corporation, Application Note 237, "Using High-Speed Transceiver Blocks in Stratix GX Devices", November 2002, ver. 1.0
[2]
ITU-T, G. .707/Y.1322, "Network node interface for the Synchronous Digital Hierarchy (SDH)", May 2002.

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 18 January 2005

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