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Design and implementation of an SDH high-speed switch
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Source with EDA Technofair Design Automation Conference Asia and South Pacific archive
Proceedings of the 2005 conference on Asia South Pacific design automation table of contents
Shanghai, China
SESSION: University design contest table of contents
Pages: 17 - 18  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
De_Hui Zhang  Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China
Quan_Liang Zhao  Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China
Jun-Gang Han  Xi'an Institute of Post and Telecommunications, Xi'an, P.R. China
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this shot paper, we propose a design of SDH High-Speed Switch, which can switch 16x16 STM-16 streams with speed at 2.488 Gbit/s. In this design a novel fabric structure was used to perform non-blocking connection of STM-1 data in any timeslot of 16-bit parallel STM-16 data rate at 155.5MB/s. The prototype of the design is implemented in Altera's StratixTM GX FPGA devices. The test results show that the prototype meets all requirements.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Altera Corporation, Application Note 237, "Using High-Speed Transceiver Blocks in Stratix GX Devices", November 2002, ver. 1.0
 
2
ITU-T, G. .707/Y.1322, "Network node interface for the Synchronous Digital Hierarchy (SDH)", May 2002.
Collaborative Colleagues:
De_Hui Zhang: colleagues
Quan_Liang Zhao: colleagues
Jun-Gang Han: colleagues

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