|
ABSTRACT
After establishing the unsatisfiability of a SAT instance encoding a typical design task, there is a practical need to identify its minimal unsatisfiable subsets, which pinpoint the reasons for the infeasibility of the design. Due to the potentially expensive computation, existing tools for the extraction of unsatisfiable subformulas do not guarantee the minimality of the results. This paper describes a practical algorithm that decides the minimal unsatisfiability of any CNF formula through BDD manipulation. This algorithm has a worse-case complexity that is exponential only in the treewidth of the CNF formula. We provide an empirical evaluation of the algorithm, highlighting its efficiency on a set of hard problems as well as its ability to work with existing subformula extraction tools to achieve optimal results.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
|
| |
3
|
SAT Benchmarks from Automotive Product Configuration, http://www-sr.informatik.uni-tuebingen.de/~sinz/DC/.
|
| |
4
|
Hans L. Bodlaender , John R. Gilbert , Hjálmtýr Hafsteinsson , Ton Kloks, Approximating treewidth, pathwidth, frontsize, and shortest elimination tree, Journal of Algorithms, v.18 n.2, p.238-255, March 1995
[doi> 10.1006/jagm.1995.1009
]
|
| |
5
|
|
| |
6
|
Renato Bruni and Antonio Sassano. Restoring satisfiability or maintaining unsatisfiability by finding small unsatisfiable subformulae. Electronic Notes in Discrete Mathematics, 9, 2001.
|
| |
7
|
|
| |
8
|
|
| |
9
|
J. R. Burch, E. M. Clarke, and D. E. Long. Symbolic model checking with partitioned transition relations. In Proceedings of the International Conference on Very Large Scale Integration, 1991.
|
| |
10
|
|
| |
11
|
|
| |
12
|
Rina Dechter. Bucket elimination: A unifying framework for probabilistic inference. In Proceedings of the 12th Conference on Uncertainty in Artificial Intelligence, pages 211--219, 1996.
|
| |
13
|
|
| |
14
|
|
| |
15
|
Holger H. Hoos and Thomas Sttzle. SATLIB: An Online Resource for Research on SAT. In I. P. Gent, H. v. Maaren, T. Walsh, editors, SAT 2000, pages 283--292. IOS Press, 2000. SATLIB is available online at www.satlib.org.
|
| |
16
|
|
| |
17
|
|
 |
18
|
Matthew W. Moskewicz , Conor F. Madigan , Ying Zhao , Lintao Zhang , Sharad Malik, Chaff: engineering an efficient SAT solver, Proceedings of the 38th conference on Design automation, p.530-535, June 2001, Las Vegas, Nevada, United States
[doi> 10.1145/378239.379017]
|
 |
19
|
Yoonna Oh , Maher N. Mneimneh , Zaher S. Andraus , Karem A. Sakallah , Igor L. Markov, AMUSE: a minimally-unsatisfiable subformula extractor, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996710]
|
| |
20
|
Christos H. Papadimitriou and David Wolfe. The complexity of facets resolved. In Proceedings of the 26th Annual Symposium on Foundations of Computer Science, pages 74--78, 1985.
|
 |
21
|
|
| |
22
|
The Annual SAT Competitions: http://www.satlive.org/SATCompetition/.
|
| |
23
|
|
| |
24
|
Fabio Somenzi. CUDD: CU Decision Diagram Package. Release 2.4.0.
|
| |
25
|
Stefan Szeider. Minimal unsatisfiable formulas with bounded clause-variable difference are fixed-parameter tractable. In Proceedings of the Nineth International Computing and Combinatorics Conference, pages 548--558. Springer Verlag, 2003.
|
| |
26
|
|
| |
27
|
H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit enumeration of finite state machines using BDDs. In Proceedings of the IEEE International Conferece on Computer Aided Design, pages 130--133, 1990.
|
 |
28
|
|
| |
29
|
Lintao Zhang and Sharad Malik. Extracting small unsatisfiable cores from unsatisfiable Boolean formula. Presented at the Sixth International Conference on Theory and Applications of Satisfiability Testing, 2003.
|
CITED BY 2
|
Andre Suelflow , Goerschwin Fey , Roderick Bloem , Rolf Drechsler, Using unsatisfiable cores to debug multiple design errors, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
|
|
|
|
|