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Redundant-via enhanced maze routing for yield improvement

Published: 18 January 2005 Publication History

Abstract

Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via after detailed routing. In this paper, we propose the first routing algorithm that considers feasibility of redundant via insertion in the detailed routing stage. Our routing problem is formulated as maze routing with redundant via constraints. The problem is transformed to a multiple constraint shortest path problem, and solved by Lagrangian relaxation technique. Experimental results show that our algorithm can find routing layout with much higher rate of redundant via than conventional maze routing.

References

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Louis K. Scheffer, "Physical CAD Changes to Incorporate Design for Lithography and Manufacturability" Proc of ASPDAC, 2004.
[2]
Y. Zorian, D. Gizopoulos, C. Vandenberg, P. Magarshack, "Guest Editors' Introduction: Design for Yield and Reliability", IEEE Trans on Design & Test of Computers, vol 21, issue 3, May 2004.
[3]
TSMC Symposium 2004.
[4]
G. A. Allan and A. J. Walto, "Automated redundant via placement for increased yield and reliability", Proc of SPIE, vol 3216, pp 114--125, 1997.
[5]
Hardy K. S. Leung, "Advanced Routing in Changing Technology Landscape", Proc of ISPD, pp. 118--121, 2003.
[6]
Naveed Sherwani, "Algorithms for VLSI Physical Design Automation", 3rd edition, Kluwer Academic Publisher, 1999.
[7]
Hai Zhou, Martin D. F. Wong, "Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation", Proc of ICCD, pp. 628--633, 1997.
[8]
Li-Da Huang, Martin D. F. Wong, "Optical Proximity Correction (OPC)-Friendly Routing", Proc of DAC, pp. 186--191, 2004.

Cited By

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  • (2019)SAQIPACM Transactions on Architecture and Code Optimization10.1145/331187916:2(1-21)Online publication date: 18-Apr-2019
  • (2019)A local optimal method on DSA guiding template assignment with redundant/dummy via insertionProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3288748(305-310)Online publication date: 21-Jan-2019
  • (2016)MCFRoute 2.0Proceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902966(87-92)Online publication date: 18-May-2016
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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 January 2005

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2019)SAQIPACM Transactions on Architecture and Code Optimization10.1145/331187916:2(1-21)Online publication date: 18-Apr-2019
  • (2019)A local optimal method on DSA guiding template assignment with redundant/dummy via insertionProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3288748(305-310)Online publication date: 21-Jan-2019
  • (2016)MCFRoute 2.0Proceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902966(87-92)Online publication date: 18-May-2016
  • (2016)Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability considerationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898088(1-6)Online publication date: 5-Jun-2016
  • (2016)Load-Aware Redundant Via Insertion for Electromigration AvoidanceProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872355(99-106)Online publication date: 3-Apr-2016
  • (2016)Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid LithographyProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872352(39-46)Online publication date: 3-Apr-2016
  • (2016)Quantum circuit physical design flow for the multiplexed trap architectureMicroprocessors & Microsystems10.1016/j.micpro.2016.02.01845:PA(23-31)Online publication date: 1-Aug-2016
  • (2015)Post-layout Redundant Via Insertion Approach Considering Multiple Via ConfigurationCircuits, Systems, and Signal Processing10.1007/s00034-015-0010-z34:10(3353-3372)Online publication date: 1-Oct-2015
  • (2013)Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rateIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217696821:1(142-147)Online publication date: 1-Jan-2013
  • (2011)Detailed RoutingVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-90-481-9591-6_6(167-188)Online publication date: 27-Jan-2011
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